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EE Times India - total search 199 articles sort by date sort by relevance
HW/SW co-dev't with focus on software 2012-01-13
Here's a discussion on the problems of hardware/software co-development from the point of view of the software designer.  
MATLAB: The sleeper ESL hit 2005-05-18
The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow.  
Cadence's 'all-in-one' tool gets skeptic reviews 2001-05-01
Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises.  
Designing a high-voltage generator circuit for HDTV 2004-02-16
POWER  
FPGAs reduce MPU power consumption 2010-04-22
The newer and better FPGA technology brings with it a whole new set of challenges for the designer. Power utilisation is one issue that moves to the forefront when designing an FPGA-based embedded system for a handheld or portable device.  
Fundamentals of core-based FPGA design (Part 1) 2011-08-22
The first instalment of this series provides an overview of FPGA processor core types—firm, hard and soft—and the pros and cons that need to be evaluated in the context of an embedded system's requirements.  
MATLAB: The sleeper ESL hit 2005-05-18
The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow.  
Shenzhen home to kindred entrepreneurial spirits 2001-04-01
Ling Shi and Dong Tao are kindred examples of a new spirit of entrepreneurialism taking root in Shenzhen, the Chinese boomtown just across the border from Hong Kong.  
Lessons in time, cost savings from iPhone 3GS 2009-06-29
A more integrated—and probably lower cost—iPhone caused one analyst to quip the 'S' in 3GS may stand for savings.  
The case for real-time visibility 2005-11-02
Good development requires good debugging, and good debugging requires good visibility. Take an inside look at what makes a good debugger and what customers should look for in their own tools.  
Virtual display glasses, up close and personal 2007-12-03
Virtual display glasses are nothing, but improvements have slimmed the package considerably and brought costs to levels more simpatico with consumer budgets.  
Complex SoCs power intent verification 2009-05-15
Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level.  
Go beyond LTE requirements, goals 2008-12-26
LTE presents a number of lofty goals, creating challenges for technology and service providers, and equipment manufacturers.  
Implement safety features in industrial system designs 2012-02-01
Know how prequalified FPGAs save substantial time in achieving product certification as worldwide safety standard requirements become increasingly complex.  
Using graph-based synthesis for FPGA timing closure 2007-07-11
The increased effects of routing on FPGA path timing requires EDA tools to understand physical properties of the target device and analyze designs during the placement process in order to achieve timing closure.  
Synthesis route starts with instructions 2001-05-01
Synthesis route starts with instructions  
A/V receiver nails cost/performance trade-off 2007-08-13
Direct Energy Amplification and Linear Temperature Compensation are two of the fundamental technological breakthroughs at the heart of the VSX1016-TXV's performance.  
DVR with PCI performance from USB 2009-03-10
Wonder 650 is the first product with hardware encoding technology needed to output television signals to a PC through USB.  
Oki, Lexra roll out prototyping boards for SoCs 2001-04-15
This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs.  
Dual regulator typology needed to power modern cellphones 2004-08-16
POWER  
Comms design activity bucks the downward trend 2001-06-16
Rollout delays, service problems and fly-by-night service providers may have dampened market conditions for DSL technology, but design activity continues at a frantic pace.  
Cut yield fallout by preventing over and under at-speed testing 2011-10-14
Learn how to overcome the problems associated with SoC at-speed testing such as over-testing and under-testing to boost yield.  
Managing single event effects in FPGAs, ASICs and processors (Part 2) 2012-01-09
This part tackles the ways to mitigate single event effects.  
SPI-S—a next-gen interface for serial physical interconnects 2006-12-18
The System Packet Interface—Scaleable (SPI-S) is the next-generation interface developed by the OIF to take advantage of serialisation of physical interconnects.  
28nm FPGAs target next-gen communication apps 2011-03-23
Xilinx Inc.'s Kintex-7 K325T FPGAs are built with 28nm technology to meet the price and power performance needs of key communications applications.  
Power management provides design simplicity for handhelds 2004-07-01
POWER  
HP and STMicroelectronics Launch "Lx" 2000-10-06
A new VLIW architecture promises to shake up the system-on-chip design world.  
Single-mask simplicity needed for SoC 2001-06-01
The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices.  
Perform fault monitoring, manage backplane power 2004-09-16
Perform fault monitoring, manage backplane power  
BlueTrack mouse revealed 2009-05-25
With this mouse, new approaches to lighting and image processing are brought to bear.  


Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

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