Power Integrity and Energy Aware Floor Planning
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2008-01-29 |
| Extreme performance and frequency are no longer dominant design goals for SoC's. Recent years have witnessed changes in microprocessors' architectures, with multi-GHz unicore CPU devices abandoned in favour of low-frequency multi-core variants, and frequency becoming a forgotten memory. |
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| Hierarchical physical design for million-gate ASICs
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2001-04-15 |
| Raw design size in million-gated ASICs can cripple physical design and timing closure and the viable solution is physical hierarchy. |
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| Driving a 32-bit RISC in an FPGA
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2002-03-01 |
| This technical article describes an optimized 32-bit RISC processor capable of running up to at least 75MHz and occupies less than 40 percent of area in an FPGA. |
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| Improving productivity with FPGA design reuse
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2000-12-01 |
| This technical article describes the most effective way to fill the productivity gap in silicon integration. |
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| Paving paths to software radio design
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2002-03-01 |
| This technical article discusses how designers must rethink their product selection strategies in their software radio architectures over a broad frequency range now that the lines between ASICs, FPGAs and DSPs are blurring. |
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| Mastering full-custom layout design
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2002-02-16 |
| This technical article assists readers in defining the various flavors of full-custom layout design for them to choose the right type of tool for the right type of job. |
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| 'Divide and conquer' with hierarchical design
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2002-03-16 |
| This technical article describes how physical synthesis alone could not present a complete solution to the challenges of advanced chip design. Therefore, as an alternative, designs must be subdivided into manageable blocks. |
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| Optimizing the RISC/DSP combo for voice over IP
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2003-11-03 |
| Extensible architectures are a way to combine RISC and DSPs, but a poor implementation can negatively affect cost and execution speed. |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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| Design Trends and EDA Tools: China & Taiwan
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2002-10-01 |
| This joint study by EE Times?sia and Gartner Dataquest conducted in the year 2002 reveals information on the latest design trends in China and Taiwan. The white paper is the result of a survey conducted by EE Times?sia on China- and Taiwan-based electronics design community across industries. |
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| Bluetooth-enabled ASICs versus standard Bluetooth chipsets
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2002-04-08 |
| This article describes Bluetooth wireless technology and its various implementations |
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| The new century of high-density functional circuits
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2001-06-01 |
| With every "electronic" product getting smaller and more powerful, manufacturing will need more innovation, denser interconnect schemes and better tools to meet the challenges ahead. |
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| Multimedia, video and imaging need FPGAs
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2004-03-16 |
| JPEG2000 and AVC offer unprecedented levels of performance but at a computational cost that favors FPGA technology over traditional processor-based solutions. |
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| Next generation router design for wire-speed packet processing
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2001-08-09 |
| This conference technical paper discusses the process of accelerated packet processing that will make future routing devices robust enough to deliver wire-speed transmission. |
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| Selecting ASICs or ASSPs for key net functions
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2003-07-16 |
| Network system design activity is accelerating with a renewed emphasis on product differentiation and cost-effectiveness. System design teams must evaluate technology options that usually lead them to choose between ASICs and ASSPs for most of the network packet processing functions they require. |
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| Platform ASICs deliver reduced cost for many applications
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2004-07-16 |
| To save time and cost, platform ASICs come with predefined and prediffused layers to which customers can add differentiations. |
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| Perform fault monitoring, manage backplane power
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2004-09-16 |
| Backplanes responsible for distributing power to multiple-card systems must be immune to individual card failures. |
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| Fine tune point-of-load regulation in DTVs
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2008-10-28 |
| Read about Point-of-Load regulators and the unique requirements of bus termination voltages. |
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| Being reasonable with design constraints
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2002-02-01 |
| This technical article describes how budgeting time and resources in developing design constraints can reduce overall product development time. |
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| Advanced ICs allow security integration
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2002-12-16 |
| Merchant-market ICs are letting designers integrate SSL and IPSec into their system and still maintain throughput. |
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| Using FPGAs for measurement, control
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2003-08-01 |
| Find out the benefits and challenges of using FPGAs in systems that require measurement and control functionality. |
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| Trends, challenges in systems design
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2005-06-16 |
| Basic system-design methodologies are changing to enable the parallel design of the FPGA and PCB for optimum system cost, performance and cycle time |
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| Speeding up internal data pipe connection
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2002-07-16 |
| The emerging 10Gbps specification promises to solve some tricky design headaches, particularly in chip-to-chip and interboard communications. |
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| Bluetooth chipmaker will ride 802.11a wave
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2001-04-15 |
| This technical article describes Cambridge Silicon Radio's move to develop an all-CMOS 802.11a chip for 54MHz wireless networking in the 5GHz band. |
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| Measuring Bugs
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2002-11-18 |
| article discusses how fixing bugs in the early stages of program development allow designers to avert potential future problems associated with extensive testing. |
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| Using cost-effective PWM controller for small power-offline apps
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2004-12-16 |
| The article presents the development of a new PWM power-supply controller IC for universal input and low-power applications. |
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| Evaluating processing options for system-on-chip integration
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2004-07-01 |
| Decisions in SoC integration has to do with the resources available and how features and bugs will be handled. |
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| Timing closure in DSM design
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2001-04-15 |
| Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale? |
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| Debug OCP designs with on-chip instrumentation
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2006-01-01 |
| Debug analysis and on-chip instrumentation are evolving to support more complex chips, addressing issues such as bus-level debug. |
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| Using automatic Emscan in high-speed PCB design
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2003-09-01 |
| Emscan claims that its system provides an efficient way of evaluating the replacement component's usability, reducing production cost without any compromise to EMI integrity. |
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Strange modes of transport and other "stuff"
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