FPGA on-chip debug with off-chip benefits
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2003-02-17 |
| This article will address some of the limitations of on-chip debug and show users an alternative that combines the best of both worlds--on-chip debug with off-chip, deep sample storage. |
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| Speeding up FPGA clock schemes
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2004-01-01 |
| One of the most important steps in the design process is to identify how many different clocks to use and how to route them. |
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| Designing digital video broadcast and wireless systems with common FPGA building blocks
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2008-02-13 |
| Common IP building blocks for FPGAs make it easier for designers to implement one system for DTV and reuse and modify the same building blocks for other data communication applications. |
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| Tap high-speed FPGA transceiver for PHY
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2007-03-28 |
| The demand for high-speed transceivers is increasing dramatically as systems are required to support higher data bandwidths, and implement a higher degree of functionality and features density. |
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| Improving productivity with FPGA design reuse
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2000-12-01 |
| This technical article describes the most effective way to fill the productivity gap in silicon integration. |
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| Designing FPGA signal-processing datapaths for SDR
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2002-04-08 |
| This article provides an overview of how several signal processing functions can be implemented in a field programmable gate array. |
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| FPGA clock trees and their efficient use
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2002-04-08 |
| This article provides description on the features of proASIC and proASICPlus' clock tree as well as its design issues and applications. |
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| Learn how FPGA pares costs in digital displays
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2005-06-16 |
| To maximize savings provided by a platform-based approach, system electronic components must be carefully selected |
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| IP devt, FPGA prototyping with SystemC/TLM
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2009-03-18 |
| Here's a design flow that starts with highly abstracted models to cycle RTL models of IP. |
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| Timing analysis tools greatly impacts a successful design
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2001-05-01 |
| Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design |
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| Analyse simultaneous switching noise in PCBs
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2007-12-16 |
| This article offers a systematic simultaneous switching noise (SSN) overview with the focus on the noise caused by FPGA output buffers. The authors offer several PCB design tips for minimising noise |
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| Trends, challenges in systems design
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2005-06-16 |
| Basic system-design methodologies are changing to enable the parallel design of the FPGA and PCB for optimum system cost, performance and cycle time |
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| Multimedia, video and imaging need FPGAs
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2004-03-16 |
| JPEG2000 and AVC offer unprecedented levels of performance but at a computational cost that favors FPGA technology over traditional processor-based solutions |
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| Using FPGAs for high-speed serial interface design
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2003-03-17 |
| FPGA provides the bandwidth and flexibility for industry leading high-speed interfaces. Its True-LVDS technology was designed to support the strict timing requirement of up to four high-speed differential I/O protocols |
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| Improving performance in wireless subsystems
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2008-02-01 |
| For operations that can benefit from parallelism, signal processing functions in wireless systems can be improved by taking advantage of FPGA fabric flexibility and embedded DSP blocks in current FPGA architectures |
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