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EE Times India - total search 42 articles sort by date sort by relevance

IP devt, FPGA prototyping with SystemC/TLM	2009-03-18
Here's a design flow that starts with highly abstracted models to cycle RTL models of IP
Achieve cache coherence in MIPS32 multi-core design	2008-12-01
Read about design methods for facilitating design reuse centred on an open standard
Real system-level design challenge: Hardware-firmware integration	2001-06-16
For today's engineering co-design, the real system challenge is the hardware/firmware integration.
Overcome design complexities in multi-core networking (Part 2)	2009-10-01
This article discusses in more detail how multi-core can be used for a new design for 4G telecommunications infrastructure and for a network offload engine for an existing SIP server.
Reusing vital verification knowledge with OVM	2010-01-13
Reuse of legacy-directed test environments is common practice. But with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects
Employ FPGA to accelerate medical imaging process	2011-09-01
Know how to use an FPGA platform and a high level synthesis tool called Impulse C to accelerate a statistical line of reaction estimation for a high-resolution PET scanner.
System integration technologies support SoC design	2001-05-08
System integration is a critical bottleneck in the development of system-on-a-chip technologies.
Charting the future of mobile digital video recorder	2006-01-16
Portable media players need sufficient headroom to accommodate different codecs in the growing multimedia content market.
Platform ASICs deliver reduced cost for many applications	2004-07-16
To save time and cost, platform ASICs come with predefined and prediffused layers to which customers can add differentiations.
The advantages of using PCB design reuse	2000-12-01
This technical article focuses on the benefits of PCB design reuse and discusses the elements that leverage the reuse methodology
Improving productivity with FPGA design reuse	2000-12-01
This technical article describes the most effective way to fill the productivity gap in silicon integration.
Extraction method verifies IP functions	2001-06-01
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process

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EE Times Asia - total search 242 articles

Clock ICs geared for PCIe devices	2012-01-27
Address hardware/software integration issues with combined prototyping solutions	2012-01-11
Broadcom CTO tackles NetLogic buy	2011-09-14
Open platform expedites IP publishing, integration	2011-09-13
Speeding up medical imaging process using FPGA	2011-09-01
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