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EE Times India - total search 121 articles sort by date sort by relevance
Outlining operation principles of PhotoMOS relays 2003-06-02
The characteristics, architecture, and typical circuit of the PhotoMOS relay control circuit, as well as ways to ensure reliability in use are discussed in this article.  
Modelling for accurate Serdes design 2007-12-16
This paper describes an algorithmic modelling methodology that gives you flexibility in modelling your serial I/O device accurately while providing you with all the IP protection you need.  
Addressing signal integrity in backplane interconnects 2005-07-18
Signal integrity is a basic requirement in deploying higher speed communications links and services  
Address SI issues in high-speed board design 2007-03-16
This article discusses some of the SI challenges and the factors associated with high-speed interface designs that are enabled with key features of a RapidIO switch.  
Improve ESD protection in cellphones 2005-10-03
Dual clamping claims to bring better electrostatic discharge immunity compared to current single ESD-protection diodes  
The ramifications of component selection 2001-08-16
Need to know what is the most important electrical specification for a connector or IC package? This article looks at what is generally the hardest problem in component selection.  
Serial ATA: Designing for high-speed storage 2005-03-16
Designing with SATA requires a new way of thinking for everyone. Here are layout rules to ensure a working implementation  
LVDS pre-emphasis boosts cable performance 2005-05-16
Moving streams of data over copper cables can be done more cost-effectively without lagging in performance  
Connectorless probes simplify digital design 2004-08-16
With connectorless probes, designers can probe their signals without having to compromise board space or signal integrity.  
A novel SBU dielectric and coating system 2001-11-01
This technical article describes a novel dielectric coating system as well as a new material that enhances thin foil use and via plugging.  
Effective interconnect space reduction formation 2001-05-16
Significant technical progress has been made with newly developed materials and with the introduction of new components, this evolution has become possible. This paper describes the benefits of using microvias.  
Design Trends and EDA Tools: China & Taiwan 2003-09-18
This joint study by EE Times?sia and Gartner Dataquest conducted in the year 2003 reveals information on the latest design trends in China and Taiwan. The white paper is the result of a survey conducted by EE Times?sia on China- and Taiwan-based electronics design community across industries.  
Package efficiency: A boost to power MOSFETs 2003-04-16
DirectFET technology has radically reduced package resistance and inductance, and facilitated a large reduction in the thermal resistance.  
Practical DFT leads to highly testable ASICs 2001-06-01
Combine classic design-for-test methodologies, such as scan and BIST, with practical DFT, to clear the path to a highly testable design  
Maximizing voice quality across 3G nets 2004-08-02
Integration of echo cancellers in the gateway delivers superior voice quality in 3G networks.  


 
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