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EE Times India - total search 88 articles sort by date sort by relevance

Use clock-gating efficiency to reduce power	2008-01-15
Clock-gating is an accepted design technique for optimising power, and can be applied at the system level.
Putting automated libraries into the flow	2001-05-01
With time-consuming and expensive process, many semiconductor firms have opted to work with independent library vendors. The solution to this problem would be to implement automatically generating cell libraries that can help ease design limitations.
Researchers team up for Java-based IP query tool	2001-05-16
A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web.
System-level multicore debugging made easy	2005-08-01
Virtual system prototypes outdo traditional ISS models in multicore SoC designs
Custom FPGA-based emulators accelerate IC design	2001-11-16
The regular, hierarchical structure that can be created in a custom FPGA means you can compile designs on a single workstation 5 to 20 times faster than traditional emulators.
A verification environment for embedded processors	2001-10-16
This technical article describes the Altera verification environment for embedded processor devices, which addresses the conflicting needs of quality versus complexity versus time.
Solving problems early on using co-verification	2004-11-16
Learn the importance and benefits of hardware and software co-verification before the physical design becomes available.
Matrix approach for on-chip interconnect	2002-04-01
This technical article describes how an innovative matrix technique can easily simplify SoC interconnect processes for complex IC designs.
ESL enables software-driven SoCs	2005-07-18
This article provides detailed information on electronic system-level design and why it is popular among technology leaders
SystemVerilog enhances assertion-based verification	2005-06-16
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how
Formal verification for IP soft core	2003-11-17
Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them.
Using ISSP technology in structured ASIC design	2003-12-16
NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm.
Improving productivity with FPGA design reuse	2000-12-01
This technical article describes the most effective way to fill the productivity gap in silicon integration.
Equivalence checking for SoC blocks	2001-11-16
This technical article explains that as custom blocks become increasingly important for SoCs, equivalence checking between transistor-level implementation and behavioral modeling become equally significant design factors.
Developing audio processor hardware with C	2002-04-16
This technical article describes a new C-based software environment capable of creating high-performance hardware designs in very tight schedules.
The advantage of using logic BIST for ASIC designs	2000-12-01
This technical paper reveals the advantage of using logic BIST for ASIC designs.
Solutions in developing Bluetooth IP	2002-05-16
This technical article discusses how to implement the Bluetooth technology in chip designs using platform-based techniques and higher abstraction.
Application engine synthesis offers new design approach	2005-06-01
Application engines have become critical functionality enablers in SoCs for complex consumer devices
Power-Sensitive Design Techniques On FPGA Devices	2001-07-03
This paper focuses on the design techniques that need to be considered for power saving when considering FPGA devices.
ALF language lets designers control libraries	2004-05-17
Without ALF, EDA tools could not overcome the deficiencies by proprietary, tool-specific and fragmentary library extensions.
Deterministic simulation of an ARM core	2001-12-01
This technical article discusses the deterministic and random testing techniques used to verify complex cores such as the ARM946E-S architecture.
Behavioral modeling accelerates for OEM requirements	2001-02-01
This technical article describes the high-level behavioral modeling that can speed-up design along the road to tapeout by identifying architectural opportunities and pitfalls.
Reducing IC design time with advanced emulation	2002-06-01
Learn an innovative way to reduce IC design time by using an advanced processor with complete SoC capabilities.
Timing closure: Hybrid optimization to the rescue	2004-08-16
Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.
Universal controller ties fate to emulation	2002-07-01
SoC design service providers are tapping the flexibility of emulation techniques to enhance chip verification and test.
Reconfigurable computing accelerates network device verification	2001-02-01
This technical paper describes the use of reconfigurable computing (RCC) coprocessor technology and its attendant software to speed the verification of a large networking device.
DFT confronts test cost in design run	2002-04-16
This technical article offers a synopsis of the challenges in SoC design, particularly with regard to test costs.
Assertion methodologies for Verilog design	2002-01-16
This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL.

---total search 88 articles, total 3 pages, The 3 Page---

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EE Times Asia - total search 846 articles

Address hardware/software integration issues with combined prototyping solutions	2012-01-11
Identifying the 4G PHY architecture design challenges	2011-12-20
Software promises speedier FPGA design	2011-12-15
Designing 3D-ICs (Part 2)	2011-12-08
RTL sol'n yields ultra low-power design	2011-11-14
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