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EE Times India - total search 162 articles sort by date sort by relevance
Wireless SDR: overcoming Onext gen handset challenges 2003-09-01
Wireless handset manufacturers must deliver products that offer expanded services; while product designers are challenged to create extremely power-efficient broadband wireless devices.  
Rapid design of media-enabled information appliances 2001-01-01
An integration platform approach can greatly facilitate the rapid development of new products, as well as successors and derivatives. The article takes a look at the design of an information appliance that may spawn many derivatives.  
Solutions in developing Bluetooth IP 2002-05-16
This technical article discusses how to implement the Bluetooth technology in chip designs using platform-based techniques and higher abstraction.  
Making RF cellular design simple 2005-11-01
The challenge in RF handsets is to consume less PCB space as more features are embedded without sacrificing performance  
Articulating hierarchical design for SoCs 2002-01-01
The unified flow for complex designs, complete with hierarchical design capabilities, is an intuitively pleasing proposition.  
Timing closure: Hybrid optimization to the rescue 2004-08-16
Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.  
Hopper hierarchical flow: Improvements for large ICs 2001-09-16
This technical article describes the Hopper software hierarchical flow implemented to maximize large, high-performance IC design.  
Application engine synthesis offers new design approach 2005-06-01
Application engines have become critical functionality enablers in SoCs for complex consumer devices  
Separate vs. integrated smart-phone components 2005-06-01
Only by weighing the trade-offs can a designer arrive at the best possible wireless-appliance solution for a specific design requirement  
Formal verification for IP soft core 2003-11-17
Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them.  
Across the flow: DFM's many faces 2005-05-16
EDA toolmakers, designers forge partnership to develop new DFM process flow  
Implementing audio codecs in configurable processors 2006-08-14
You can implement audio codecs in hard-wired logic, on general-purpose microprocessors, on DSPs, or on configurable microprocessors. Tensilica compares the approaches for system developers implementing the codecs in SoCs.  
SystemVerilog enhances assertion-based verification 2005-06-16
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how  
Noise analysis catches hidden timing flaws 2002-03-16
This technical paper discusses how with shrinking process technologies, designers must cope with escalating crosstalk noise effects that impact high-speed SoCs prior to manufacturing.  
COT design flow validates SoCs 2002-05-01
This technical article details the approach two chip companies used to validate a COT (customer-owned tool) flow from beginning to end resulting in a complete working silicon.  


 
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