Signal integrity issues rise with 500Mbps rates
|
2004-09-01 |
| SoC designs with data transfer rates beyond 500Mbps fall in a gap between traditional design methods and the proposed chip-package-virtual board co-design method |
|
| Grasp SystemVerilog testbench debug, analysis
|
2008-10-16 |
| The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation |
|
| Extracting value from integrating power management
|
2006-12-20 |
| As System-on-Chips (SoC) provide more to the system in terms of the level of integration, performance and battery-life, integration of power management into the SoC becomes a necessity in the industry |
|
| Integrating power management solutions into SoCs
|
2006-04-18 |
| This article describes power management options available for SoC design engineers, with techniques for easier and faster integration of analogue IP functions |
|
| Complex SoCs breed new design strategies
|
2001-03-01 |
| Building effective system-on-chip (SoC) devices are nudging electronic engineers and designers today as they are asked to confront the diverse circuit types that can coexist on a single chip |
|
| Design with Verification: Not an Oxymoron
|
2007-11-05 |
| In SoC development, the relatively new concept and practice of design with verification promises multiple benefits |
|
| An integrated approach to PCI verification in SoCs
|
2001-11-01 |
| This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs |
|
| Plato unwraps router for huge systems-on-chip
|
2001-06-01 |
| This technology news article describe the Plato Design System's SoC routing device to eliminate capacity bottlenecks |
|
| Functional verification of 10M-gate SoCs
|
2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites |
|
| Oki, Lexra roll out prototyping boards for SoCs
|
2001-04-15 |
| This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs |
|
| The work flow of a block-based design team
|
2001-12-01 |
| In the block-based design flow, engineers work with blocks comprising thousands of cells rather than with the individual cells, thus providing a higher level of abstraction necessary for dealing with complex multi-million-gate SoC designs |
|
| Matrix approach for on-chip interconnect
|
2002-04-01 |
| This technical article describes how an innovative matrix technique can easily simplify SoC interconnect processes for complex IC designs |
|
| DFT confronts test cost in design run
|
2002-04-16 |
| This technical article offers a synopsis of the challenges in SoC design, particularly with regard to test costs |
|
| Universal controller ties fate to emulation
|
2002-07-01 |
| SoC design service providers are tapping the flexibility of emulation techniques to enhance chip verification and test |
|
| Transaction-based method supports co-verification
|
2004-04-01 |
| This paper describes how engineers doing SoC verification can be more efficient by using a single, reconfigurable verification system, applications and a unified methodology |
|
|
|
|IIC-China
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment