Moving into the wireless design mainstream with RF SiP
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2006-09-05 |
| This article provides a discussion on designing an RF SiP layout and the benefits of such. |
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| Fitting last year's IP to today's processes
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2001-06-01 |
| Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry. |
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| Deal with complexity of hardware design project management
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2011-10-05 |
| Read about an approach to combat the problems of IP management, remote site performance, inconsistent deployment, IP reuse and designer collaboration. |
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| ASIC generation revamped for IP reuse
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2001-06-01 |
| ASIC generation revamped for IP reuse |
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| Unifying hardware, software verification
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2009-03-05 |
| Explore the need for a unified platform for both hardware and embedded software development. |
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| Developing a design methodology for embedded memories
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2001-01-01 |
| Developing a design methodology for |
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| Advanced multi-Vdd methods to reduce power
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2006-09-30 |
| Address key power considerations using an advanced, virtually flat multi-Vdd methodology. |
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| Knowing Android's strengths and weaknesses
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2011-10-14 |
| Here's a look at the techniques for exploiting Android's strengths and managing its limitations, especially in hard real-time, mission-critical systems. |
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| Techniques for using latches
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2011-08-15 |
| Learn about the advantages and disadvantages of latches over flip flops. |
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| SystemVerilog reference verification methodology: VMM adoption
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2006-09-04 |
| The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification. |
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| MATLAB: The sleeper ESL hit
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2005-05-18 |
| The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
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| Cadence's 'all-in-one' tool gets skeptic reviews
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2001-05-01 |
| Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises. |
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| Ensuring the accuracy of third-party IP
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2006-10-01 |
| The best and most unambiguous measure of functional correctness is the extent to which IP has been validated in silicon production. The article discusses the most basic need of every chip designer—functionally correct IP. |
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| MATLAB: The sleeper ESL hit
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2005-05-18 |
| The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
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| Targeting 32-bit CPUs for industrial applications
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2006-05-01 |
| There is a quiet revolution occurring in industrial environments, as 32-bit CPUs and networking work their way into even the most deeply embedded devices. |
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| Lessons in time, cost savings from iPhone 3GS
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2009-06-29 |
| A more integrated—and probably lower cost—iPhone caused one analyst to quip the 'S' in 3GS may stand for savings. |
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| The case for real-time visibility
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2005-11-02 |
| Good development requires good debugging, and good debugging requires good visibility. Take an inside look at what makes a good debugger and what customers should look for in their own tools. |
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| A primer on Bluetooth Low Energy (Part 1)
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2011-08-08 |
| This two-part series gives an introduction to Bluetooth Low Energy (BLE) and its use in energy-constrained applications. |
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| Complex SoCs power intent verification
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2009-05-15 |
| Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level. |
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| Simulating and debugging multi-core behaviour
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2006-03-04 |
| Debugging a single processor is hard enough. What can you do when there are multiple processors inside one chip? One answer is to simulate the system before the actual hardware is ready. |
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| Developing embedded Linux device drivers for a system-on-chip device
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2004-04-22 |
| IIC-China/ESC-China 2004 7 Conference Proceedings 139 |
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| Why use SONOS memory for eflash
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2011-10-13 |
| Read about the features of silicon-oxide-nitride-oxide-silicon memory technology that make it ideally suited for embedded Flash. |
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| CMOS radios span RF to millimeter wave frequencies
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2004-11-16 |
| CMOS radios span RF to millimeter wave frequencies |
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| HD DVD player pushes the performance envelope
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2007-04-01 |
| When Toshiba set out to develop a second generation of the HD-1A, it was with the intention of reducing cost of the system, not change the features. |
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| A primer on Bluetooth Low Energy (Part 2)
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2011-09-21 |
| The second instalment of this two-part series tackles the Bluetooth software stack partition. |
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| Choosing the right silicon TV tuner IC
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2011-11-16 |
| Learn about the technical issues involved in the selection of TV tuner. |
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| Managing the transition from parallel to serial storage interfaces
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2003-09-16 |
| Managing the transition from parallel to serial storage interfaces |
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| Extending hybrid/EV battery packs' lifetime (Part 1)
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2011-12-21 |
| Learn how to prevent charge imbalance that can diminish a battery pack's total capacity and potentially damage the pack. |
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| The partitioning challenge of ASIC design into multiple FPGAs
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2010-02-12 |
| Partitioning a large ASIC design into multiple FPGAs can be challenging. Doing some upfront planning and selecting the right tool flow can make achieve a thoroughly verified ASIC and first-silicon success. |
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| OCP's role in multi-core designs
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2008-11-19 |
| Learn about the Open Core Protocol that is expected to address today's multi-core problems. |
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Strange modes of transport and other "stuff"
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