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Use EE Times-India online search engine to quickly find technical articles, product news, current industry trends and application notes to aid your design projects and enhance your market edge.
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EE Times India - total search 162 articles sort by date sort by relevance
SystemVerilog reference verification methodology: VMM adoption 2006-09-04
The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification.  
Complex SoCs power intent verification 2009-05-15
Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level.  
Bridging the system to RTL continuum 2005-05-19
The article discusses the need for system-level design and verification methodologies. It also discusses the need for tools and technologies that support RTL to system level transition.  
DSP power propels next-generation wireless 2001-04-15
The enhancements of wireless design offers new opportunities with tough tech challenges for designers. However, DSPs will remain a fundamental part of wireless design.  
Automate formal verification for OCP 2008-07-15
This article discusses the automation of FV for bus protocols like Open Core Protocol (OCP).  
MATLAB: The sleeper ESL hit 2005-05-18
The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow.  
DVD recorder systems present complex design challenges 2004-07-16
DVD recorder systems present complex design challenges  
New thinking needed amid runaway test costs 2001-04-15
There is a need to achieve test-cost reductions that rival the reductions in wafer fabrication costs to ensure continued growth of semiconductor markets. ATE should not wait for someone else to do it.  
Automate formal verification for Open Core Protocol 2008-09-24
The automation of formal protocol verification using VIPs enables an exhaustive verification of critical IP interfaces.  
Analogue, mixed-signal connectivity IP at 65nm, below 2007-05-07
Here are some considerations in designing high-performance analogue/mixed-signal circuits with standard deep subµm CMOS technologies.  
Simulate RFIC designs with substrate parasitics 2008-09-29
Prepare and correlate substrate parasitics for 65nm low-power RF CMOS applications.  
ASIC generation revamped for IP reuse 2001-06-01
ASIC generation revamped for IP reuse  
Emulation or prototyping for silicon success? 2001-04-15
With the high-stakes financial and time-to-market risks involved in designing ICs, which verification method is necessary for first-pass silicon success?  
IP devt, FPGA prototyping with SystemC/TLM 2009-03-18
Here's a design flow that starts with highly abstracted models to cycle RTL models of IP.  
Analog, mixed-signal design flow found wanting 2001-06-16
Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper.  

Embedded Design India - total search 65 articles
Low power CapSense design using CY8C22x45 2010-03-09
The partitioning challenge of ASIC design into multiple FPGAs 2010-02-12
Timing closure methodology for advanced FPGA designs 2009-12-29
Product tutorial: Reducing development time for infotainment apps 2009-11-27
Perform high-speed, low-cost prototyping of ASIC designs 2009-10-30
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Power Design India - total search 14 articles
i.MX35 multimedia power consumption under Linux 2009-08-04
Opportunity to win on different design fronts 2009-06-23
Early power analysis with CPF 2008-10-31
Power supply sequencing in ICs 2008-10-23
Choose the right multi-processor development tools for power efficiency 2008-10-08
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EE Times Asia - total search 2601 articles
Wafer probe card facility rises in Singapore 2010-03-12
Wireless comm processor ups security with WPA2 2010-03-12
RF range extender combines PA, LNA, switches 2010-03-11
Embeddable LTE modem core supports 150Mbit/s 2010-03-09
Host/slave controller supports up to 44 IO pins 2010-03-05
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