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EE Times India - total search 62 articles sort by date sort by relevance
Smart partitioning in WiMAX radios shows design challenges (1) 2006-10-13
This article in a two-part series provides background information on the traditional partitioning in WiMAX radios.  
Eliminate substrate coupling in MS SOCs 2009-03-16
Read about substrate noise and learn how to address it using isolation techniques and other CAD solutions.  
Scaling JTAG to evolving embedded needs 2006-08-09
JTAG adoption and integration requires a strategy across multiple development disciplines to ensure a standard approach that you can re-use and build on in later generations of the product. This article describes how JTAG is used in various generations of system development and design.  
Handling the challenges of interleaving high-speed ADCs 2009-11-19
Synchronously sampling analogue signals with time-interleaved ADCs at billions of times per second is a technical challenge. Overcome the hurdles and know the advancements in interleaving methodologies.  
Virtual display glasses, up close and personal 2007-12-03
Virtual display glasses are nothing, but improvements have slimmed the package considerably and brought costs to levels more simpatico with consumer budgets.  
CMOS radios span RF to millimeter wave frequencies 2004-11-16
CMOS radios span RF to millimeter wave frequencies  
PI-IPM cuts motor drive design time, risk 2003-08-18
power  
Managing the transition from parallel to serial storage interfaces 2003-09-16
Managing the transition from parallel to serial storage interfaces  
Improve top-level simulation for switching DC-DC converters 2006-04-16
This article presents an optimized solution strategy to improve top-level simulation for switching DC-DC converters.  
Complex SoCs breed new design strategies 2001-03-01
Building effective system-on-chip (SoC) devices are nudging electronic engineers and designers today as they are asked to confront the diverse circuit types that can coexist on a single chip.  
Uncovering hidden chip costs 2007-10-22
For some consumer electronics manufacturers, ICs are the single largest contributor to finished-goods costs. An understanding of the chip supplier's cost structures can bolster the OEM's negotiating position.  
Analogue behavioural models reduce LSI verification time 2008-08-14
Selective use of analogue behavioural models instead of SPICE elements can greatly speed up simulation.  
Protel upgrades P-CAD package 2001-04-15
This article describe the enhancements in Protel's P-CAD line of products, which includes schematic capture, signal-integrity analysis, library management and PCB placement.  
Lower the cost of intelligent power control with FPGAs 2007-12-15
Combining a programmable solution with an industry-standard processor core can save time, money, and real estate.  
A critical test of SoC memory strategies 2004-08-02
A critical test of SoC memory strategies  


 
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