RF SiP technology moves to wireless design mainstream(2)
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2006-08-28 |
| This article discusses how an ideal RF SiP flow must manage, replicate, and control post-layout simulations. |
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| Polar modulation in mobile PA design
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2004-02-02 |
| POWER |
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| Translating MATLAB-to-C, Part 3: Code generation, verification
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2009-03-06 |
| Know the complex functions and the role C interface constraints play in the translation process. |
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| Making virtual prototyping better than designing with hardware (Part 1)
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2010-06-25 |
| The use of virtual prototypes prior to hardware delivery has well-documented benefits. This article focuses on the virtual prototype benefits after physical prototype availability. |
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| Complex designs call for verification
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2010-06-14 |
| Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging. |
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| Verification challenges of embedded memory devices
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2006-08-14 |
| This article discusses the verification challenges faced by embedded memory designers as the technology moves towards integration. |
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| Specifying DDR requirements with PCB routing tools
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2006-09-25 |
| Alternative methods for specifying high-speed timing requirements have advantages over traditional methods as shown in this guideline for PCB design. |
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| How formal MDV can take out IP integration uncertainty
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2012-01-25 |
| Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics. |
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| Design flip-chip packages with integrated USB 3.0
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2011-05-23 |
| Learn about the use of IE3D to design a four-layer package that has a USB 3.0 interface. |
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| Flow is shaky for programmable SoCs
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2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
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| Emulation or prototyping for silicon success?
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2001-04-15 |
| With the high-stakes financial and time-to-market risks involved in designing ICs, which verification method is necessary for first-pass silicon success? |
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| Optimising software using TLM virtual platform
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2011-12-07 |
| Find out how transaction level modelling 2.0 was used to produce an executable system model and, subsequently, execute software to analyse functional aspects contributing to overall system level performance. |
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| Building prototype user interfaces on a PC
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2003-09-01 |
| Building prototype user interfaces on a PC |
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| Using PCB routing tools in DDR and hi-speed timing requirements
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2006-09-24 |
| The article discusses a new approach in specifying DDR and high-speed timing requirements by using printed circuit board routing rules. |
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| How to model, apply capacitor-bypass networks (4)
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2007-10-15 |
| This paper examines some surprising interactions that appear when modelling a real bypass network and presents solutions for minimising them to suit the desired application. |
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| Autosar: detecting design flaws early on
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2010-08-16 |
| Autosar terminologies and related processes are rather comprehensive, and they differ substantially from older, established design methodologies. |
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| Managing single event effects in FPGAs, ASICs and processors (Part 1)
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2011-12-28 |
| As dimensions fall below 90 nm, all electronics, including ASICs and FPGAs get affected with single event effects, with faults ranging from logical errors to changes in data to latchups. |
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| Developing a comprehensive test, support plan
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2009-07-24 |
| This article discusses Mirabilis Design's experience in developing a comprehensive test and support plan. |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. |
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| Startup preps 5Gbps backplane transceiver
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2001-06-16 |
| In a bid to build a better bit pipe on the backplane, Accelerant Networks is preparing to roll out a proprietary CMOS transceiver that harnesses multilevel signaling technology. |
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| Optimizing DSPs for wireless world
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2001-04-15 |
| Complexities in next-generation requirements is taxing the capabilities of traditional DSP technology and design methodologies, causing a need for industry business models to be drastically redefined. |
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| More prototyping tips
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2003-09-16 |
| More prototyping tips |
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| Interactions in modelling a capacitor-bypass network
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2007-10-15 |
| Bypass capacitors may not have the glam of ICs, but they are vital to proper circuit performance. Understand how to properly model and apply them. |
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| Interactions in modelling a capacitor-bypass network
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2007-10-15 |
| Bypass capacitors may not have the glam of ICs, but they are vital to proper circuit performance. Understand how to properly model and apply them. |
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| Back to the basics: The art of algorithm implementation
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2005-10-11 |
| The article discusses how a common interface performing interactive algorithm design decreases inefficiencies and provides a single programming platform to design, prototype and deploy intelligent devices. |
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| Using cost-effective Zigbee
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2008-02-16 |
| The explosive growth expected in device connection is being driven by the emergence of new open standards like IEEE 802.15.4 and Zigbee,and cost plays an important role in system viability. This article discusses a low-cost way of implementing wireless functionality. |
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| SystemVerilog enhances assertion-based verification
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2005-06-16 |
| ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how |
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| Timing analysis tools greatly impacts a successful design
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2001-05-01 |
| Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design. |
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| Mastering signal integrity fundamentals
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2001-12-16 |
| The author shows why a solid foundation in signal integrity issues and analysis is a must for IC- and PCB-design engineers. The article describes the necessary learning required. |
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| Measuring impedance in disk drive circuits
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2004-08-02 |
| By performing a virtual TDR, impedance variations with different trace and stack-up dimensions can be studied. |
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Strange modes of transport and other "stuff"
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