Verification reuse ensures predictable design
|
2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes. |
|
| Improving accuracy with model-delay library systems
|
2002-03-01 |
| This technical article describes the advantage of implementing SPDM (scalable polynomial delay model) over NLDM (non-linear delay model) in attaining accurate deep-submicron modeling results. |
|
| Timing closure in DSM design
|
2001-04-15 |
| Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale? |
|
| System level tools enable complex design solutions
|
2007-06-01 |
| The article presents a design methodology developed at Synopsys that has been successfully applied in developing a base-band subsystem for various wireless systems such as GSM, W-CDMA, DAB and MBOA-UWB. |
|
| Wireless Palm Pilot connection for LabVIEW
|
2002-07-16 |
| Learn a portable solution designed for field engineers working and traveling between plants to get various data and information on critical operating conditions. |
|
| Embedded Linux and the Law
|
2002-11-01 |
| The rising popularity of Linux, combined with perceived cost savings, has spurred many embedded developers to consider a real-time Linux variant as an alternative to a traditional RTOS. |
|
| Functional verification of 10M-gate SoCs
|
2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites. |
|
| Enhancing sound quality with DACs
|
2002-06-01 |
| Audio engineers can maximize their multimedia project's system quality by employing digital-to-analog techniques into their designs. |
|
| Lower costs through design tool performance
|
2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
|
| Simulate CAN bus comms in ECU networks
|
2007-11-16 |
| ECUs are often used in a network and communicate with each other over the CAN bus. Simulate these messages to verify the functionality of an ECU. |
|
| Assertion methodologies for Verilog design
|
2002-01-16 |
| This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL. |
|
| Equivalence checking for SoC blocks
|
2001-11-16 |
| This technical article explains that as custom blocks become increasingly important for SoCs, equivalence checking between transistor-level implementation and behavioral modeling become equally significant design factors. |
|
| Address verification issues with scalable methods
|
2007-04-10 |
| This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams. |
|
| Tap model-based design in DDC development
|
2007-03-23 |
| Model-based design provides an environment for creating executable specifications, which provide a high-level view of the design that can be used to explore system-level analysis and trade-offs, and detect potential design and implementation errors. |
|
| Simulating UWB RFICs
|
2006-08-04 |
| Ansoft and UMC describe new technologies for RF and analogue design, and verification within established design flows. Circuits from an ongoing project to develop an ultrawideband MB-OFDM radio are used to demonstrate new technological capabilities. |
|
| Design and verification with Cadence's Virtuoso AMS Designer
|
2005-06-01 |
| This article explains the different 'use model' requirements for the simulator to accommodate its users, the mixed-signal system architect, the model developer, the analog and digital design engineers and the verification engineer |
|
| Silicon prototyping verifies IP functions
|
2001-06-01 |
| SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next. |
|
| Solution space analysis for high-speed design
|
2001-06-22 |
| Up-front SI analysis can drive placement and routing while providing a viable alternative to the old "route-analyze-fix" approach of yesteryear. |
|
Strange modes of transport and other "stuff"
|
|
|IIC-China
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment