Verification reuse ensures predictable design
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2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes. |
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| Timing analysis tools greatly impacts a successful design
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2001-05-01 |
| Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design. |
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| Enhancing sound quality with DACs
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2002-06-01 |
| Audio engineers can maximize their multimedia project's system quality by employing digital-to-analog techniques into their designs. |
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| Mastering signal integrity fundamentals
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2001-12-16 |
| The author shows why a solid foundation in signal integrity issues and analysis is a must for IC- and PCB-design engineers. The article describes the necessary learning required. |
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| Improving accuracy with model-delay library systems
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2002-03-01 |
| This technical article describes the advantage of implementing SPDM (scalable polynomial delay model) over NLDM (non-linear delay model) in attaining accurate deep-submicron modeling results. |
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| Functional verification of 10M-gate SoCs
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2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites. |
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| Simulate CAN bus comms in ECU networks
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2007-11-16 |
| ECUs are often used in a network and communicate with each other over the CAN bus. Simulate these messages to verify the functionality of an ECU. |
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| Address verification issues with scalable methods
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2007-04-10 |
| This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams. |
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| Timing closure in DSM design
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2001-04-15 |
| Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale? |
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| SystemVerilog enhances assertion-based verification
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2005-06-16 |
| ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how |
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| Embedded Linux and the Law
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2002-11-01 |
| The rising popularity of Linux, combined with perceived cost savings, has spurred many embedded developers to consider a real-time Linux variant as an alternative to a traditional RTOS. |
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| Solution space analysis for high-speed design
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2001-06-22 |
| Up-front SI analysis can drive placement and routing while providing a viable alternative to the old "route-analyze-fix" approach of yesteryear. |
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| Measuring impedance in disk drive circuits
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2004-08-02 |
| By performing a virtual TDR, impedance variations with different trace and stack-up dimensions can be studied. |
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| Wireless Palm Pilot connection for LabVIEW
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2002-07-16 |
| Learn a portable solution designed for field engineers working and traveling between plants to get various data and information on critical operating conditions. |
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| Tap model-based design in DDC development
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2007-03-23 |
| Model-based design provides an environment for creating executable specifications, which provide a high-level view of the design that can be used to explore system-level analysis and trade-offs, and detect potential design and implementation errors. |
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