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EE Times India - total search 45 articles sort by date sort by relevance
Verification IP reuse for complex networking ASICs 2008-09-18
Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse.  
Windows NT And Windows 2000 For Real-Time Applications 2001-07-03
For many reasons, Windows NT, NT Embedded and Windows  
Post-silicon validation methodology for DSPs 2008-11-11
Read about post-silicon validation that is carried out on the first fabricated ICs with a true system built around it.  
Process design kits take aim at custom ICs 2001-04-15
This technical article describes Cadence Design Systems' process design kits for 0.25µm and 0.18µm process simulations.  
Optimizing ASIC design flow for SoPCs 2001-05-01
System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly.  
Developing a design methodology for embedded memories 2001-01-01
Developing a design methodology for  
Dynamic system simulation 2001-03-01
High-fidelity simulations of dynamic embedded systems can be invaluable. This follow-up to "Modelling Dynamic Systems" (August 2000) presents some techniques and algorithms you might find useful.  
C-Language for FPGA acceleration of embedded software 2006-03-31
Learn how computationally intensive algorithms can be written, analysed, and optimised for increased performance in FPGAs.  
Extraction method verifies IP functions 2001-06-01
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.  
Building prototype user interfaces on a PC 2003-09-01
Building prototype user interfaces on a PC  
Verification firm starts partners program 2001-04-15
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.  
Simulation reveals embedded-algorithm behavior 2001-06-01
interest here is in assembling a  
Optimizing DSPs for wireless world 2001-04-15
Complexities in next-generation requirements is taxing the capabilities of traditional DSP technology and design methodologies, causing a need for industry business models to be drastically redefined.  
Embedded test complicates SoC realm 2001-03-01
SoC devices today implement a variety of specialized microelectronic functions. Those functions, sometimes with embedded systems, typically comprise of hardware or software design objects  
Syntax raises RTL abstraction level 2001-05-16
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.  


 
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