Full-chip verification for building nanometer memories
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2002-05-01 |
| Verification tools can greatly facilitate memory design, where designers face a combination of evolving circuit complexity and increasing size in dealing with massive memory arrays |
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| What makes an optimal SOC verification strategy
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2011-03-15 |
| An optimal SOC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: 'what to verify', 'how to verify' and 'are we done |
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| Go beyond verification tool limits for analogue/RF designs
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2008-09-15 |
| Know the limits of today's design approaches, and how the challenges of analogue/RF design and verification may be reduced by new EDA tools and techniques |
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| Automate formal verification for Open Core Protocol
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2008-09-24 |
| The automation of formal protocol verification using VIPs enables an exhaustive verification of critical IP interfaces |
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| Address verification issues with scalable methods
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2007-04-10 |
| This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams |
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| Full-chip verification for analogue/mixed-signal ICs
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2006-08-14 |
| Here's how verification to detect design flaws helps you succeed with an analogue/mixed signal chip |
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| Design and verification strategies for complex systems
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2006-06-12 |
| This is the first of a two-part article that discusses conventional embedded design and verification techniques, and the trade-offs associated with each approach |
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| Planning the verification project
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2006-01-01 |
| Project management is all about planning and execution. "Good" verification involves a formulaic model to drive the whole verification project with an executable plan |
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| Moving towards system-level design and verification success
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2006-10-09 |
| Transaction-based system verification helps design teams through the complete system verification process and enables them to maximise VIP use |
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| Hurdling 45nm software-to-silicon verification problems
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2009-08-10 |
| The growing role of verification complexity and embedded software in the chip-development process presents many challenges to tool vendors and system designers alike |
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| Complex designs call for verification
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2010-06-14 |
| Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging |
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| Verification challenges of embedded memory devices
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2006-08-14 |
| This article discusses the verification challenges faced by embedded memory designers as the technology moves towards integration |
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| Applying constrained-random verification to microprocessors
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2007-12-10 |
| This article proposes an object-oriented solution for processor verification challenges |
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| Transaction-based method supports co-verification
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2004-04-01 |
| This paper describes how engineers doing SoC verification can be more efficient by using a single, reconfigurable verification system, applications and a unified methodology |
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| Accelerating verification closure for complex SoCs, IPs
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2008-10-24 |
| The complexity of today's SoCs creates the need for advanced verification methods that go beyond simulation-based approaches |
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| Reconfigurable computing accelerates network device verification
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2001-02-01 |
| This technical paper describes the use of reconfigurable computing (RCC) coprocessor technology and its attendant software to speed the verification of a large networking device |
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| How to deal with formal verification issues
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2010-03-30 |
| Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick |
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| Build OCP verification components
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2009-02-16 |
| Know the two key aspects of OCP that were adopted for the architecture of a verification component |
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| Co-verification of an RTOS in a SoC
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2002-01-16 |
| This technical article discusses the evolution of co-verification in HW/SW development as it has evolved from an optional requirement to a mandatory one in SoC designs |
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| Unifying hardware, software verification
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2009-03-05 |
| Explore the need for a unified platform for both hardware and embedded software development. |
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| Verification beyond base classes
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2009-02-24 |
| Know the details of VMM applications, which are built on top of the VMM base classes. |
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| Use processor-driven tests for functional verification
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2006-10-04 |
| This article discusses processor driven test bench methods in detail and presents their strengths and weaknesses. It examines the inherent value of combining PDT with traditional HDL test benches. |
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| Identification chips bring fingerprint verification a step further
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2006-04-05 |
| A new fingerprint identification chip takes ID verification technology to the next level |
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| Verification tech captures automotive expertise
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2005-09-01 |
| The automotive industry calls for modern verification techniques as the proliferation of electronic gadgetry adds to rising IC complexity in cars |
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| Single-chip analogue, digital TV ASIC verification
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2007-06-13 |
| Here are some questions and considerations on next-generation ATV and DTV ASICs. |
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| Understand verification coverage with formal analysis
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2011-05-02 |
| Know how formal coverage can be used to evaluate constraints and proofs. |
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| Understanding enterprise system level (ESL) verification (1
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2006-11-20 |
| The article gives an in-depth discussion of ESL including its history, present applications and future developments, among others. |
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| Analogue behavioural models reduce LSI verification time
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2008-08-14 |
| Selective use of analogue behavioural models instead of SPICE elements can greatly speed up simulation. |
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| Design constraint verification, validation
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2008-09-26 |
| Learn some useful tips for using software that can manage, verify and create design constraints. |
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| IC verification: Coverage vs. qualification
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2009-04-30 |
| EDA needs functional qualification, a product that is fundamentally different from existing coverage technologies. |
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