Formal verification of an MPEG decoder chip
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2001-06-01 |
| This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip |
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| Moving towards system-level design and verification success
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2006-10-09 |
| Transaction-based system verification helps design teams through the complete system verification process and enables them to maximise VIP use |
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| Full-chip verification for analogue/mixed-signal ICs
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2006-08-14 |
| Here's how verification to detect design flaws helps you succeed with an analogue/mixed signal chip |
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| Verification platform for complex designs
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2007-12-31 |
| The article provides an insight on verification problems that semiconductor companies face in today's complex design. It suggests verification platforms to overcome the challenges |
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| Tackling physical verification below 90nm
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2005-05-02 |
| The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them |
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| Emulation solves verification challenge
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2007-12-16 |
| Sun Microsystems shares experiences of latest generation hardware-based verification systems used to develop its recently launched Ultrasparc T2 processor |
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| Automate formal verification for Open Core Protocol
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2008-09-24 |
| The automation of formal protocol verification using VIPs enables an exhaustive verification of critical IP interfaces |
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| Software verification, debug in the MPSoC era
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2007-06-12 |
| A new breed of programming and debug solutions is required to help programmers with the specific software verification challenges in MPSoC |
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| Cut design time, cost with early verification
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2010-02-11 |
| Verification of algorithm-intensive systems is a long, costly process. In this article, we'll explain three practical approaches to early verification |
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| Full-chip verification for building nanometer memories
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2002-05-01 |
| Verification tools can greatly facilitate memory design, where designers face a combination of evolving circuit complexity and increasing size in dealing with massive memory arrays |
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| Verification challenges of embedded memory devices
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2006-08-14 |
| This article discusses the verification challenges faced by embedded memory designers as the technology moves towards integration |
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| Verification beyond base classes
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2009-02-24 |
| Know the details of VMM applications, which are built on top of the VMM base classes. |
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| Design and verification with Cadence's Virtuoso AMS Designer
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2005-06-01 |
| This article explains the different 'use model' requirements for the simulator to accommodate its users, the mixed-signal system architect, the model developer, the analog and digital design engineers and the verification engineer |
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| Verification and validation
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2001-06-01 |
| Every product has defects. Finding them as early in the development process as possible is definitely something to strive for. |
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| IC verification: Coverage vs. qualification
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2009-04-30 |
| EDA needs functional qualification, a product that is fundamentally different from existing coverage technologies. |
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