Automate formal verification for OCP
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2008-07-15 |
| This article discusses the automation of FV for bus protocols like Open Core Protocol (OCP). |
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| A verification environment for embedded processors
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2001-10-16 |
| This technical article describes the Altera verification environment for embedded processor devices, which addresses the conflicting needs of quality versus complexity versus time |
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| Get the most out of IDEs for hardware design and verification
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2011-06-06 |
| Read about the current growth and future prospects of IDEs in hardware verification, as well as its implications for hardware design |
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| Verification and validation
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2001-06-01 |
| Every product has defects. Finding them as early in the development process as possible is definitely something to strive for. |
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| Design and verification with Cadence's Virtuoso AMS Designer
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2005-06-01 |
| This article explains the different 'use model' requirements for the simulator to accommodate its users, the mixed-signal system architect, the model developer, the analog and digital design engineers and the verification engineer |
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| Software verification for non-safety critical embedded designs
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2009-04-06 |
| Know how non-safety critical systems can also benefit from the standards in aerospace and automotive industries. |
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| Reusing vital verification knowledge with OVM
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2010-01-13 |
| Reuse of legacy-directed test environments is common practice. But with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects. |
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| Design and verification strategies for complex systems (2
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2006-06-19 |
| Virtual system prototypes can result in better products, shorter development times, and lower development costs. |
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| Incremental DRC for chip verification
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2009-05-18 |
| Incremental DRC provides real time results, allowing you to fix or waive errors and validate them before the entire DRC run is complete. |
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| Ultrasparc III passes physical verification
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2002-09-16 |
| Sun Microsystem's new processor succeeds in its quest to make optimal use of the die area and power budget to achieve highest performance. |
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| Boost functional verification with SLEC
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2009-02-09 |
| SLEC has the capability to formally verify RTL implementations against a specification in C/C++ or System C. |
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| Analysis tools speed up design debug, verification
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2005-09-01 |
| Learn about developments in logic analyzers that open up new dimensions in speed and performance |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| External process augments verification infrastructure
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2006-09-25 |
| The paper discusses how to connect an external (unrelated) process to a simulator environment using inter-process communication. |
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| Design Issues And Verification Challenges For Home Networks
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2001-03-27 |
| This paper looks into some of the challenging questions and considerations when choosing the right processor for the Home Network application design. |
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| Functional verification of 10M-gate SoCs
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2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites. |
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| Modeling, verification of backplane press-fit vias
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2004-10-01 |
| Look at active and passive components of a system differently to push higher data rates through backplane channels. |
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| Spectrum analysis key to speed up 3G verification
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2003-10-01 |
| Time-to-market, competitiveness and market share are important considerations on the increasingly aggressive 3G market. |
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| Multi-language SoC verification for multi-site projects
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2008-02-18 |
| Know how to address design issues that involve .managing and automating much of the SoC level integration that comes from various sites. |
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| Translating MATLAB-to-C, Part 3: Code generation, verification
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2009-03-06 |
| Know the complex functions and the role C interface constraints play in the translation process. |
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| Verification issues for reconfigurable IP
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2005-03-01 |
| To improve reusability, IP providers are developing clever ways to configure IP and enable semicustom IP blocks while reducing the potential to break the code |
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| Power distribution for deep-submicron SoC designs
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2001-05-01 |
| Power grid verification is becoming an imperative in deep-submicron design |
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| Use Spice tools to simulate large-scale analogue/RF circuits
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2007-11-28 |
| Here's a taste of the power that analogue fastSPICE simulators can bring to large-scale analogue/RF verification |
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| Employing intelligently integrated physical design
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2011-01-17 |
| Learn about an improved approach to physical verification based on intelligent point integration with physical design |
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| Technical intro to functional qualification, Part 3
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2009-04-13 |
| Read about assertion which is treated like a checker in the verification environment in the context of functional qualification |
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| Bridging the system to RTL continuum
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2005-05-19 |
| The article discusses the need for system-level design and verification methodologies. It also discusses the need for tools and technologies that support RTL to system level transition |
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| Generating testbed for wireless sensor nets
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2004-11-01 |
| Embedded system-based testbeds for wireless sensor networks are useful for protocol and related algorithm verification |
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| Verifying your low-power designs
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2007-08-27 |
| Here are some of the power reduction techniques used in today's chip designs, the pitfalls of each, and how to set up low-power verification |
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| Timing closure in DSM design
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2001-04-15 |
| Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale |
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| Achieving certified IP quality efficiently
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2008-09-26 |
| Complete formal functional verification can enable IP providers to certify highest IP quality cost-effectively and with high productivity |
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Strange modes of transport and other "stuff"
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