Grasp SystemVerilog testbench debug, analysis
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2008-10-16 |
| The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation |
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| Applying front-end design methodologies
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2006-10-23 |
| The article discusses the set of targeted solutions for logic design teams aiming at reducing the overall risks associated with front-end design and verification. It focuses on the "four forces of change"—power, verification, test and physical effects |
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| Moving beyond advanced design geometries
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2008-08-01 |
| Design verification will play a major role in reducing design cost and improving new product yields and product platforms |
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| Extraction method verifies IP functions
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2001-06-01 |
| To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process |
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| Simulate embedded hardware acceleration
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2007-04-18 |
| The HES system provides solutions for the different verification stages, including hardware acceleration simulation, SoC HW/SW acceleration co-verification and hardware prototype verification |
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| Simulating UWB RFICs
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2006-08-04 |
| Ansoft and UMC describe new technologies for RF and analogue design, and verification within established design flows. Circuits from an ongoing project to develop an ultrawideband MB-OFDM radio are used to demonstrate new technological capabilities |
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| Transaction-based simulation using SystemC/SCV
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2005-03-16 |
| Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results |
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| Interoperable tools ease equivalence checking
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2003-08-18 |
| Without postponing the verification cycle and risk to design integrity, an automated setup allows users to solve new verification problems |
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| How formal MDV can take out IP integration uncertainty
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2012-01-25 |
| Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics |
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| Emulation wins over FPGA prototyping
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2008-01-16 |
| System-level verification solutions require the power of emulation to address the opposing forces of increasing complexity and shrinking design schedules |
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| Architect, design, implement, and verify low-power digital ICs
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2007-01-29 |
| To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs |
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| Incremental design poses programmable advantage
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2003-12-01 |
| Incremental design lets engineers make debug design changes faster during verification and allows for a late-arriving design spec change all without major delays to the project timeline |
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| Evolution of manufacturing closure for advanced nodes (Part 3)
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2011-02-21 |
| Learn how performing signoff DRC/DFM verification within the place and route environment affects the design flow and improves time to closure |
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| Design, verify 802.11a 5GHz WLAN systems
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2005-07-18 |
| Delve into the IEEE 802.11a physical layer and the integrated software/hardware design flow for a typical IC design and verification |
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| Improve simulation studies with 3D animation
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2011-06-28 |
| Read about the use of 3D animation in simulation-centric workflows to augment early verification activities, such as those used in model-based design |
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| Verifying automatically generated flight code
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2011-11-23 |
| Know how to measure code efficiency and perform code verification activities using MATLAB and Simulink product family Release 2011b, featuring the Embedded Coder for flight code generation |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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| Prototype, debug targets ARC-based SoCs
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2001-05-01 |
| This article describes the Aptix and ARC Core team-up to configure a verification environment that enables developers to prototype full SoCs in near-real-time conditions |
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| Developing a video emulation environment
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2002-01-01 |
| This technical article describes the relevance of employing verification and emulation to video communications design and the IC capable of providing standards-based motion video encoding and decoding for real-time video conferencing apps |
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| Power mode technologies verify today's SoCs
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2008-02-27 |
| Five technologies – PDML specification, power-aware simulation, structural power checks, power-related assertions, and formal analysis of the power-control logic – provide outstanding checking and coverage while saving half of the power verification time |
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| Complying with PCI Express
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2008-12-11 |
| Read about a test approach, which employs third party VIP and is based on metrics-driven verification |
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| Boost productivity with ESL techniques
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2007-08-14 |
| The increased complexity that comes with 90nm and smaller geometries have led to a myriad of severe challenges, including HW/SW co-design, power management and verification. An ESL methodology offers a viable solution to these challenges |
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| Power mode technologies verify today's SoCs
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2008-02-27 |
| Five technologies – PDML specification, power-aware simulation, structural power checks, power-related assertions, and formal analysis of the power-control logic – provide outstanding checking and coverage while saving half of the power verification time |
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| Emulation or prototyping for silicon success?
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2001-04-15 |
| With the high-stakes financial and time-to-market risks involved in designing ICs, which verification method is necessary for first-pass silicon success |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process |
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| Using OVM configuration classes
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2010-04-28 |
| This technical paper is a testimony to the fact that configuration classes, when used properly, greatly improve the configurability and adaptability of a verification environment |
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| Universal controller ties fate to emulation
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2002-07-01 |
| SoC design service providers are tapping the flexibility of emulation techniques to enhance chip verification and test |
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| Reduce development costs through software partitioning
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2006-07-10 |
| This article guarantees resources while simplifying verification |
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| Balancing load and customising content at Layer 7
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2006-05-03 |
| This third article in a series covers load balancing mechanisms and test and verification |
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| Building threat simulator for multi-port radar and warfare systems
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2011-12-05 |
| Here's a look at the process of developing a test platform to evaluate the performance of a four-port unit under test. The results provide significant benefits from technical and operational perspectives. |
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Strange modes of transport and other "stuff"
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