Technical intro to functional qualification
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2009-04-03 |
| Know how functional qualification can meet the challenge of delivering functionally correct silicon on time and on budget. |
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| Virtual vehicle: Wiring harnesses
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2009-03-23 |
| Here's a methodology that contains the necessary steps to ensure the creation of robust wiring harnesses. |
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| Performing high-level synthesis
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2010-03-11 |
| It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesise a design that does not work. |
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| Improving quality of aerospace design
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2009-07-02 |
| Know how to achieve design efficiency through the reuse of models across various phases of the design process. |
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| Understanding clock domain crossing issues
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2007-12-24 |
| The article describes the main issues that can possibly occur whenever there is a clock domain crossing, and also gives solutions for these issues. |
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| Berkeley spin-off to spread use of Ptolemy tools
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2001-06-16 |
| Enhancements are on their way for Agile Design Inc.'s Ptolemy hierarchical simulation tools to boost engineering designs. |
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| Using GreenPAK to design, program custom chip in minutes
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2011-11-09 |
| GreenPAK 1 is like a super-small mixed-signal FPGA that you can design and program in just a few minutes and that costs only a few cents. |
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| We Need a New Approach to Accurately Simulate Large Circuits
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2007-04-30 |
| The options available for accurately verifying design behaviour, especially post layout, are very limited. SPICE can rarely read large netlists, and FastSPICE is not accurate enough where precision is critical. |
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| Algorithmic synthesis boosts efficiency
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2009-01-02 |
| Read about algorithmic synthesis which moves the creation of application engines to a higher level of abstraction. |
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| Understand programmable electrical rule checking
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2008-12-03 |
| Know how to check the robustness of a design at schematic and layout levels against various electronic design rules. |
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| Fitting last year's IP to today's processes
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2001-06-01 |
| Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry. |
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| Solutions towards PCIe compliance and interoperability
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2008-02-01 |
| In the last five years, PCIe technology has become the dominant interconnect protocol across the market. However, non-compliant and non-interoperable devices are prevalent. This article discusses the issues of PCIe compliance and interoperability. This article presents a solution to the challenges faced by the PCIe market. |
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| Biometrics systems now recognize multiple traits
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2001-06-01 |
| Many companies are turning to biometrics to truly recognize authorized users through unique, non-transferable and non-duplicatable traits, such as a face, voice or fingerprint. |
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| ASIC generation revamped for IP reuse
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2001-06-01 |
| ASIC generation revamped for IP reuse |
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| Low power design specification from RTL to GDSII
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2007-07-09 |
| Management of static power consumption requires the use of new design techniques that fall outside the capabilities of existing HDLs. |
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| Developing a design methodology for embedded memories
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2001-01-01 |
| Developing a design methodology for |
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| Researchers team up for Java-based IP query tool
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2001-05-16 |
| A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web. |
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| Avoiding RTL coding mistakes
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2011-10-26 |
| Here's a discussion on RTL coding styles that lead to increased design cycle time and unnecessary complexity during design closure. |
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| How to calculate CPU utilisation
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2004-08-02 |
| Is your chip fast enough? Is it too fast? Systems engineers might be paying for more chip than they need, or they may be dangerously close to over-taxing their current processor. Take the guesswork out of measuring processor utilisation levels. |
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| Use Multi-Vt to cut leakage power in embedded SoC
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2011-08-16 |
| Here's a multi-threshold voltage flow technique that does not require embedded SoC architecture changes. |
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| Improve A/MS simulator analysis with hardware-generated data
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2008-09-17 |
| Power up systems by combining simulation with real-world, hardware-generated data acquired using leading-edge instrumentation. |
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| Get to know Model Checking
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2004-03-01 |
| Model checking has proven to be a successful technology to verify requirements and design for a variety of real-time embedded and safety-critical systems. Here's how it works. |
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| Finding bugs in embedded C software
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2009-08-11 |
| This technical article explains how automated techniques such as pattern-based static code analysis, runtime memory monitoring, unit testing and flow analysis can be used together to find bugs in an embedded C application. |
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| C++ backed for system-level design
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2001-05-16 |
| The industry must solve the problems of a synthesizable and verifiable C++ subset that has extensibility despite language constraints and lack of transportable libraries. |
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| Abstraction for control-dominated designs
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2009-02-12 |
| Here's an article that disproves the idea that abstractions in ESL design are not applicable to a large subset of designs. |
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| Characterising mould compounds with acoustic microscopy
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2009-10-23 |
| There are two different sets of material characteristics that can be measured by an acoustic microscope. One is the acoustic impedance. The second is the acoustic attenuation, the degree to which the material absorbs ultrasound. |
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| Translating MATLAB-to-C
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2008-09-19 |
| This is part 1 of a series that discusses the translation of MATLAB to C communications and other applications. |
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| Managing multi-Vt, multi-voltage domain timing/temp inversion
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2012-01-05 |
| As we move to 65 nm and below, it is important to choose the libraries corresponding to the lowest temperature PVT because of temperature inversion effects where the delay of the cell actually decreases with increase in temperature. |
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| Reduce code devt cost using traceability tools
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2011-12-22 |
| Know how to create an RTM and maintain it throughout the course of a project, despite the inevitable development challenges along the way. |
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| Implement safety features in industrial system designs
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2012-02-01 |
| Know how prequalified FPGAs save substantial time in achieving product certification as worldwide safety standard requirements become increasingly complex. |
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Strange modes of transport and other "stuff"
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