Ultrasparc III passes physical verification
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2002-09-16 |
| Sun Microsystem's new processor succeeds in its quest to make optimal use of the die area and power budget to achieve highest performance. |
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| Modeling, verification of backplane press-fit vias
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2004-10-01 |
| Look at active and passive components of a system differently to push higher data rates through backplane channels. |
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| Boost functional verification with SLEC
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2009-02-09 |
| SLEC has the capability to formally verify RTL implementations against a specification in C/C++ or System C. |
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| Analysis tools speed up design debug, verification
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2005-09-01 |
| Learn about developments in logic analyzers that open up new dimensions in speed and performance |
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| External process augments verification infrastructure
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2006-09-25 |
| The paper discusses how to connect an external (unrelated) process to a simulator environment using inter-process communication. |
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| Verification issues for reconfigurable IP
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2005-03-01 |
| To improve reusability, IP providers are developing clever ways to configure IP and enable semicustom IP blocks while reducing the potential to break the code |
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| Applying front-end design methodologies
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2006-10-23 |
| The article discusses the set of targeted solutions for logic design teams aiming at reducing the overall risks associated with front-end design and verification. It focuses on the "four forces of change"—power, verification, test and physical effects |
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| Moving beyond advanced design geometries
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2008-08-01 |
| Design verification will play a major role in reducing design cost and improving new product yields and product platforms |
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| Grasp SystemVerilog testbench debug, analysis
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2008-10-16 |
| The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation |
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| Interoperable tools ease equivalence checking
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2003-08-18 |
| Without postponing the verification cycle and risk to design integrity, an automated setup allows users to solve new verification problems |
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| Transaction-based simulation using SystemC/SCV
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2005-03-16 |
| Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results |
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| Extraction method verifies IP functions
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2001-06-01 |
| To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process |
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| Verifying your low-power designs
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2007-08-27 |
| Here are some of the power reduction techniques used in today's chip designs, the pitfalls of each, and how to set up low-power verification |
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| Architect, design, implement, and verify low-power digital ICs
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2007-01-29 |
| To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs |
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| Timing closure in DSM design
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2001-04-15 |
| Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale |
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