| How to generate C code automatically
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2011-09-13 |
| Automatically generating readable and portable C code from your MATLAB algorithms is an easy and efficient way to speed up the system design to implementation workflow. |
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Using the PF_RING for improved lossless packet capturing
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2009-10-23 |
| Here's how you can improve lossless network packet capturing with libpcap by using the PF_RING kernel patch. |
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| Design patterns for high availability
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2002-08-02 |
| It is possible to achieve five-nines reliability with everyday commercial-quality hardware and software. The key is the way in which these components are combined. |
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| Benefits of hardware abstraction layers
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2011-11-14 |
| Find out how hardware abstraction layers can be used to reduce much of the risk, cost, and time associated with developing, maintaining, and updating a test system. |
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| Process design kits take aim at custom ICs
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2001-04-15 |
| This technical article describes Cadence Design Systems' process design kits for 0.25µm and 0.18µm process simulations. |
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| The partitioning challenge of ASIC design into multiple FPGAs
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2010-02-12 |
| Partitioning a large ASIC design into multiple FPGAs can be challenging. Doing some upfront planning and selecting the right tool flow can make achieve a thoroughly verified ASIC and first-silicon success. |
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| An introduction to model checking
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2005-02-16 |
| An introduction to model checking |
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| Board tools unite for enhancements
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2001-06-01 |
| Leading EDA companies bare their design enhancements for existing PCB design products. |
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| Mobile devices' new roles need new tools
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2004-01-01 |
| Mobile devices' new roles need new tools |
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| Performing cost-effective headset design, test
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2010-06-24 |
| The consumer market for telephone headsets is noted for its innovative products and its fast pace. Here's how you can perform a cost-effective headset design and test. |
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| Library generators employ optical correction at cell level
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2001-03-01 |
| This technology article discusses the enhancement of cell-based designs with the evolution of EDA. |
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| Pushing power forward with a common power format
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2006-11-05 |
| The invention of a complete and consistent Common Power Format presents an industry-wide solution to the complicated deployment of low-power design techniques. |
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| Reusable models trim software costs
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2001-05-01 |
| The cost of developing embedded real-time software can be reduced by using an architecture that supports integration of software components and their behavior, and reconfiguration of component behavior at executable-code level. |
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| Hardware/software integration: Reducing the gap
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2011-03-28 |
| Read about compressing the HW/SW integration gap when using FPGA prototypes. |
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| Analog, mixed-signal design flow found wanting
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2001-06-16 |
| Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper. |
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| Improve FPGA-based ASIC prototyping
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2009-01-13 |
| Know how to overcome the challenge of connecting all the logic blocks both within an FPGA and across multiple FPGA devices. |
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| Capture, communicate power-efficient design
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2009-01-13 |
| Read about a 'low-power kit' that enables teams with and without power expertise to adopt advanced design techniques. |
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| Finding that elusive bug
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2010-11-29 |
| Read about the challenge of detecting and correcting the elusive functional defects that unavoidably arise in the design of complex SoC devices. |
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| FPGA-to-ASIC integration provides flexibility in auto MCUs
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2006-12-08 |
| The primary benefit of using MCUs has been high level system integration combined with relatively low cost. However, there are hidden costs associated with these devices well beyond the unit price. |
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| Employ SPARK for secure code dev't (Part 2)
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2012-01-23 |
| Learn how SPARK can be used to cost-effectively develop high-security systems. |
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| Validating netlist reduction, circuit extraction
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2010-01-15 |
| A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this technical article. |
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| Open source hardware
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2002-12-02 |
| This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers. |
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| The benefits of creating patterns
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2010-05-25 |
| As design nodes drop below 45nm, design rules are exploding in number and complexity, making design rule checking (DRC) harder and lengthier. |
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| SuperHyway provides SoC backbone
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2000-12-01 |
| Recent technology improvements have made it cost-effective to integrate components previously connected on a PCB onto a single piece of silicon. These so-called system-on-a-chip (SoC) devices generally comprise most of the blocks commonly found on a computer motherboard plus some application-specific intellectual property (IP). This means design issues that were formerly the province of systems designers are now within the realm of the chip architect. As a result, interconnection schemes common at the system and network level, such as packet switching, must now be considered at the SoC level. |
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| The need for software component testing
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2009-07-29 |
| This article addresses the need for the software component testing in embedded systems because software now makes up 90 per cent of the value of the embedded system devices. |
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| Your guide to choosing hardware IP
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2006-02-03 |
| Designing your own chip is hard enough without having to worry about your third-party IP supply. This guide helps ASIC and ASSP designers through the minefield of evaluating and selecting hardware IP for their important projects. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Shift from FPGAs for prototype to ASICs for production
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2011-12-16 |
| The idea of migrating an FPGA design into an ASIC can be overwhelming to a design team, but careful planning can significantly ease the process. |
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| Optical outdos copper in InfiniBand tests
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2008-07-01 |
| High-performance optical interconnect cables designed to enable computing clusters to scale out substantially further than existing 24AWG copper cables were recently on the market. This article looks at the test configuration for a new InfiniBand optical cable from Intel. |
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| Filter banks: Principles, techniques
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2009-02-20 |
| Read about filter banks and learn how to implement them with high-level synthesis tools. |
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Strange modes of transport and other "stuff"
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