Bridging the system to RTL continuum
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2005-05-19 |
| The article discusses the need for system-level design and verification methodologies. It also discusses the need for tools and technologies that support RTL to system level transition |
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| Use Spice tools to simulate large-scale analogue/RF circuits
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2007-11-28 |
| Here's a taste of the power that analogue fastSPICE simulators can bring to large-scale analogue/RF verification |
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| Emulation wins over FPGA prototyping
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2008-01-16 |
| System-level verification solutions require the power of emulation to address the opposing forces of increasing complexity and shrinking design schedules |
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| Technical intro to functional qualification, Part 3
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2009-04-13 |
| Read about assertion which is treated like a checker in the verification environment in the context of functional qualification |
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| Simulate embedded hardware acceleration
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2007-04-18 |
| The HES system provides solutions for the different verification stages, including hardware acceleration simulation, SoC HW/SW acceleration co-verification and hardware prototype verification |
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| Simulating UWB RFICs
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2006-08-04 |
| Ansoft and UMC describe new technologies for RF and analogue design, and verification within established design flows. Circuits from an ongoing project to develop an ultrawideband MB-OFDM radio are used to demonstrate new technological capabilities |
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| Achieving certified IP quality efficiently
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2008-09-26 |
| Complete formal functional verification can enable IP providers to certify highest IP quality cost-effectively and with high productivity |
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| Generating testbed for wireless sensor nets
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2004-11-01 |
| Embedded system-based testbeds for wireless sensor networks are useful for protocol and related algorithm verification |
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| Complying with PCI Express
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2008-12-11 |
| Read about a test approach, which employs third party VIP and is based on metrics-driven verification |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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| Developing a video emulation environment
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2002-01-01 |
| This technical article describes the relevance of employing verification and emulation to video communications design and the IC capable of providing standards-based motion video encoding and decoding for real-time video conferencing apps |
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| Incremental design poses programmable advantage
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2003-12-01 |
| Incremental design lets engineers make debug design changes faster during verification and allows for a late-arriving design spec change all without major delays to the project timeline |
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| Boost productivity with ESL techniques
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2007-08-14 |
| The increased complexity that comes with 90nm and smaller geometries have led to a myriad of severe challenges, including HW/SW co-design, power management and verification. An ESL methodology offers a viable solution to these challenges |
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| Universal controller ties fate to emulation
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2002-07-01 |
| SoC design service providers are tapping the flexibility of emulation techniques to enhance chip verification and test |
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