Power mode technologies verify today's SoCs
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2008-02-27 |
| Five technologies – PDML specification, power-aware simulation, structural power checks, power-related assertions, and formal analysis of the power-control logic – provide outstanding checking and coverage while saving half of the power verification time |
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| Design, verify 802.11a 5GHz WLAN systems
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2005-07-18 |
| Delve into the IEEE 802.11a physical layer and the integrated software/hardware design flow for a typical IC design and verification |
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| Emulation or prototyping for silicon success?
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2001-04-15 |
| With the high-stakes financial and time-to-market risks involved in designing ICs, which verification method is necessary for first-pass silicon success |
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| Prototype, debug targets ARC-based SoCs
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2001-05-01 |
| This article describes the Aptix and ARC Core team-up to configure a verification environment that enables developers to prototype full SoCs in near-real-time conditions |
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| Balancing load and customising content at Layer 7
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2006-05-03 |
| This third article in a series covers load balancing mechanisms and test and verification |
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| Understanding clock domain crossing issues
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2007-12-24 |
| The article describes the main issues that can possibly occur whenever there is a clock domain crossing, and also gives solutions for these issues. |
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| Performing high-level synthesis
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2010-03-11 |
| It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesise a design that does not work. |
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| Understand programmable electrical rule checking
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2008-12-03 |
| Know how to check the robustness of a design at schematic and layout levels against various electronic design rules. |
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| Fitting last year's IP to today's processes
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2001-06-01 |
| Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry. |
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| Berkeley spin-off to spread use of Ptolemy tools
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2001-06-16 |
| Enhancements are on their way for Agile Design Inc.'s Ptolemy hierarchical simulation tools to boost engineering designs. |
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| Solutions towards PCIe compliance and interoperability
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2008-02-01 |
| In the last five years, PCIe technology has become the dominant interconnect protocol across the market. However, non-compliant and non-interoperable devices are prevalent. This article discusses the issues of PCIe compliance and interoperability. This article presents a solution to the challenges faced by the PCIe market. |
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| We Need a New Approach to Accurately Simulate Large Circuits
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2007-04-30 |
| The options available for accurately verifying design behaviour, especially post layout, are very limited. SPICE can rarely read large netlists, and FastSPICE is not accurate enough where precision is critical. |
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| Technical intro to functional qualification
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2009-04-03 |
| Know how functional qualification can meet the challenge of delivering functionally correct silicon on time and on budget. |
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| The benefits of developing tests with models
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2009-08-19 |
| This article explains how virtual testing, based on system simulation and model-based design, reduces the risk of uncovering errors late in the process. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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