Optimizing IP integration
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2010-08-12 |
| A fundamental shift has occurred in SoC design. This shift has largely gone unnoticed and has introduced significant unnecessary costs and inefficiencies into the design process. |
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| Picking a RapidIO switch
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2009-03-12 |
| Here's an outline of the factors to consider when deciding which switch to use for embedded systems. |
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| Important principles for practical analogue BIST
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2011-08-01 |
| Understand the principles of analogue BIST remain, which are still a mystery to most engineers, especially analogue-circuit designers. |
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| Advanced simulation eases UWB RFIC design flow (1)
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2005-12-21 |
| Designing an MB-OFDM UWB radio is easier for SoC designers when high-performance circuit simulation is combined with reliable electromagnetic extraction in a single RF design. |
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| Real system-level design challenge: Hardware-firmware integration
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2001-06-16 |
| For today's engineering co-design, the real system challenge is the hardware/firmware integration. |
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| Ensuring smart grid meter security
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2011-01-10 |
| Learn about a secret key management strategy for Addressing the security of meters in emerging smart grid applications. |
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| Polar modulation in mobile PA design
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2004-02-02 |
| POWER |
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| Guarding critical systems with MISRA C++
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2009-09-22 |
| This article demonstrates how the MISRA C++ language subset mitigates the insecurities within the C++ language in an efficient, cost-effective manner. |
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| Making multi-core viable for medical electronics
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2011-10-28 |
| This article discusses the validation of safety claims for systems running on multi-core processors, as well as OS characteristics that can facilitate multi-core migration. |
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| Simplifying adaptive filter design in echo cancellers
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2003-04-01 |
| Traditionally,echocancellation |
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| Making virtual prototyping better than designing with hardware (Part 1)
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2010-06-25 |
| The use of virtual prototypes prior to hardware delivery has well-documented benefits. This article focuses on the virtual prototype benefits after physical prototype availability. |
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| Ikos lawsuit against Axis turns more complex
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2001-04-15 |
| Is the Ikos lawsuit strictly 'black and white' or is it tied to a takeover bid? This technical news article describes that issue against Axis Systems, which deals about the emulation patents of both companies. |
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| Increase visibility in FPGA prototypes and emulators
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2006-03-07 |
| The article suggests visibility enhancement techniques for FPGA prototypes and emulators that help locate, isolate and understand the causes of error symptoms. |
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| Perform high-speed, low-cost prototyping of ASIC designs
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2009-10-30 |
| A "typical" ASIC design cycle is in the order of 9 to 18 months, while the window of opportunity for the introduction of a product using this device can be as little as two to four months. |
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| The Big Thaw: An Agile approach for software certification
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2011-10-07 |
| This approach involves continuous performance of the activities that are affected by a change, to keep all artifacts up to date and to preserve the complete system's certifiability. |
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| Flow is shaky for programmable SoCs
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2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
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| Optimising software using TLM virtual platform
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2011-12-07 |
| Find out how transaction level modelling 2.0 was used to produce an executable system model and, subsequently, execute software to analyse functional aspects contributing to overall system level performance. |
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| What the next transistor will be like
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2011-08-01 |
| Here's a comprehensive discussion on the race is on to redefine the transistor. |
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| High Availability Design For Embedded Systems
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2001-04-03 |
| In the post-PC era, the role of smart devices is expanding every |
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| Spiral inductor modelling for RF ICs
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2006-04-17 |
| This article examines a number of issues when using simulation software, including substrate effects, 3D conductors, conductor losses, frequency effects, current return, extraction of model parameters, and convergence of simulation. |
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| Technical intro to functional qualification, Part 2
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2009-04-08 |
| Read about functional qualification and how it is related to mutation analysis. |
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| Integrating Power Awareness into IC Design
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2007-03-01 |
| A single-file common power format (CPF), by including and supporting advanced low-power techniques, can help insure that the more efficient IC designs are also producing more power-efficient IC end products. |
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| Optical beats copper in Infiniband tests
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2008-07-01 |
| A new range of high-performance optical interconnect cables designed to enable computing clusters to scale out substantially further than existing 24AWG copper cables has recently become available. This article looks at the test configuration for a new Infiniband optical cable from Intel. |
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| Deal with complexity of hardware design project management
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2011-10-05 |
| Read about an approach to combat the problems of IP management, remote site performance, inconsistent deployment, IP reuse and designer collaboration. |
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| Demystify power gating, stop leakage cold
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2008-11-06 |
| Power gating is a technique that can address the power challenges of today's nanometer IC designs. |
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| COT design flow validates SoCs
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2002-05-01 |
| This technical article details the approach two chip companies used to validate a COT (customer-owned tool) flow from beginning to end resulting in a complete working silicon. |
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| How to automate stress tests in silicon devices
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2004-03-01 |
| Stress testing consists of exposing a product to harsher conditions to overwhelm the device in different ways to quickly flush-out errors. |
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| Use timing-accurate system-level models
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2007-03-28 |
| A virtual system prototype provides a software simulation-based model of the electronic system that allows design teams to improve design productivity, reduce time-to-market and decrease risk. |
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| Power grid analysis on IR drop and electromigration
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2004-02-16 |
| IC designers can no longer assume that their Vdd and Vss grids have been designed correctly. They must perform analysis to understand how robust their power distribution methodology really is. |
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| Speed-up FPGA design process with early defect discovery
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2006-02-16 |
| Having better upfront visibility into possible defects in HW/SW interaction can prevent the need for FPGA re-spins. |
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Strange modes of transport and other "stuff"
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