| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages |
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Total Power Optimization in RTL-to-GDSII Implementation Flow
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2007-03-12 |
| This paper describes the most significant power dissipation and distribution considerations throughout the entire RTL-to-GDSII design flow. It introduces the capabilities required of a true low-power design environment that addresses these power considerations |
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| Bridging the system to RTL continuum
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2005-05-19 |
| The article discusses the need for system-level design and verification methodologies. It also discusses the need for tools and technologies that support RTL to system level transition |
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| Approaching RTL implementation with chip synthesis
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2010-03-01 |
| Chip synthesis outperforms traditional synthesis because it can synthesise and optimise the whole chip at once, as opposed to forcing the designer to split the design up into a large number of sub-blocks that need to be stitched back together again for physical design. |
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| Low power design specification from RTL to GDSII
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2007-07-09 |
| Management of static power consumption requires the use of new design techniques that fall outside the capabilities of existing HDLs. |
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| Cadence's 'all-in-one' tool gets skeptic reviews
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2001-05-01 |
| Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises |
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| SystemVerilog reference verification methodology: VMM adoption
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2006-09-04 |
| The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification |
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| Functional verification of 10M-gate SoCs
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2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites |
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| The need for an EDA API
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2001-05-01 |
| There are a lot of skepticism with Cadence's IE (Integration Ensemble) tool-with capabilities that include floorplanning, RTL synthesis, placement, routing, extraction and analysis. The arguments for a single tool that encompasses all these features are compelling, but will the tools live up to engineer's expectations |
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| Hardware design needs hardware design languages
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2009-06-19 |
| Read about the experiences in RTL market that are applicable to ESL |
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| Top-down analysis critical for power-aware design success
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2007-04-13 |
| At RTL, and even above RTL, power reduction can have the significant effect on chip and package costs, battery life and market share of electronic products |
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| Complex SoCs power intent verification
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2009-05-15 |
| Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level |
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| Boost functional verification with SLEC
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2009-02-09 |
| SLEC has the capability to formally verify RTL implementations against a specification in C/C++ or System C |
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| Choosing the right design flow model with integrated architecture
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2004-02-02 |
| Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged |
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| IP devt, FPGA prototyping with SystemC/TLM
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2009-03-18 |
| Here's a design flow that starts with highly abstracted models to cycle RTL models of IP |
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