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EE Times India - total search 14 articles sort by date sort by relevance

Grasp SystemVerilog testbench debug, analysis	2008-10-16
The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation
SystemVerilog reference verification methodology: VMM adoption	2006-09-04
The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification.
SystemVerilog enhances assertion-based verification	2005-06-16
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how
MATLAB: The sleeper ESL hit	2005-05-18
The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow
MATLAB: The sleeper ESL hit	2005-05-18
The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow
Address mixed-signal design issues with assertion-based verification	2011-11-03
Know the challenges in analogue/mixed-signal verification and learn how assertion-based method can address them.
How formal MDV can take out IP integration uncertainty	2012-01-25
Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics.
An in-depth look at ESL	2011-04-18
Here's a look at the past progression of design entry methods and the fundamental motivations behind the progressions.
Get the most out of IDEs for hardware design and verification	2011-06-06
Read about the current growth and future prospects of IDEs in hardware verification, as well as its implications for hardware design.
Speed up processor verification with testbench infrastructure reuse	2011-09-01
Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times.
Reusing vital verification knowledge with OVM	2010-01-13
Reuse of legacy-directed test environments is common practice. But with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects.
Build OCP verification components	2009-02-16
Know the two key aspects of OCP that were adopted for the architecture of a verification component.
Mixed-signal simulation in design, verification	2005-07-01
Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification
Boost productivity with ESL techniques	2007-08-14
The increased complexity that comes with 90nm and smaller geometries have led to a myriad of severe challenges, including HW/SW co-design, power management and verification. An ESL methodology offers a viable solution to these challenges.

---total search 14 articles, total 1 pages, The 1 Page---

EE Times Asia - total search 188 articles

Protocol transactors tout faster SoC verification	2012-01-03
Perform assertion-based verification in mixed-signal design	2011-11-03
Overcome challenges of ASIC/SoC prototyping with FPGAs	2011-10-24
Accelerate processor verification through testbench infrastructure reuse	2011-09-01
Design suite supports 28nm 7 series	2011-07-11
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