Assertion methodologies for Verilog design
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2002-01-16 |
| This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL |
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| Tips for compiling software to gates
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2005-07-01 |
| VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages |
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| A faster way to run Reed Solomon decoders
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2001-01-01 |
| This technology news describes the new Reed-Solomon (RS) decoder architecture that can process multiple symbols per clock cycle. |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Open source hardware
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2002-12-02 |
| This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers. |
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| Developing a design methodology for embedded memories
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2001-01-01 |
| Developing a design methodology for |
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| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| The advantage of using logic BIST for ASIC designs
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2000-12-01 |
| This technical paper reveals the advantage of using logic BIST for ASIC designs. |
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| Synthesize SoCs using C-based design flow
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2001-08-01 |
| This is a case study in which an SoC was synthesized for Columns Ltd using a C-based design flow. |
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| Board simulation expands debug scope
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2001-08-01 |
| The paper provides a basic tutorial on board simulation and explains its advantages in improving debugging early in the design stage. |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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