Back to the language roots
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2005-01-02 |
| It's not time for the revolution yet. Traditional hardware-description languages have specific features that make them superior to software programming languages; although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL |
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| Tips for compiling software to gates
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2005-07-01 |
| VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages |
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| Assertion methodologies for Verilog design
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2002-01-16 |
| This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL |
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| Compiling software to gates
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2005-01-01 |
| Are VHDL and Verilog past their prime, soon to be replaced by C-like design languages such as System C, Handel-C, and others? Professor Ian Page thinks a change is at hand |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. |
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| A faster way to run Reed Solomon decoders
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2001-01-01 |
| This technology news describes the new Reed-Solomon (RS) decoder architecture that can process multiple symbols per clock cycle. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| Get the most out of IDEs for hardware design and verification
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2011-06-06 |
| Read about the current growth and future prospects of IDEs in hardware verification, as well as its implications for hardware design. |
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| Developing a design methodology for embedded memories
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2001-01-01 |
| Developing a design methodology for |
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| Address mixed-signal design issues with assertion-based verification
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2011-11-03 |
| Know the challenges in analogue/mixed-signal verification and learn how assertion-based method can address them. |
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| Employ FPGA to accelerate medical imaging process
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2011-09-01 |
| Know how to use an FPGA platform and a high level synthesis tool called Impulse C to accelerate a statistical line of reaction estimation for a high-resolution PET scanner. |
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| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
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| Open source hardware
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2002-12-02 |
| This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers. |
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| Speed up processor verification with testbench infrastructure reuse
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2011-09-01 |
| Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| Translating MATLAB-to-C, Part 3: Code generation, verification
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2009-03-06 |
| Know the complex functions and the role C interface constraints play in the translation process. |
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| Shift from FPGAs for prototype to ASICs for production
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2011-12-16 |
| The idea of migrating an FPGA design into an ASIC can be overwhelming to a design team, but careful planning can significantly ease the process. |
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| Using LTE on FPGAs
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2009-02-19 |
| Read about LTE's features and know how FPGA may address the increased processing demands of this specification. |
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| Tackle team-based FPGA design
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2006-03-02 |
| Now that FPGA chips are large and all-encompassing it makes sense that they're no longer solo development efforts. This expert from Lattice Semiconductor describes how teams of developers can work on one FPGA cooperatively. |
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| An integrated approach to PCI verification in SoCs
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2001-11-01 |
| This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs. |
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| Co-design method enables speech recognition SoC
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2002-09-16 |
| Two STMicroelectronics design engineers use a system-level design flow based on the CoWare N2C method to create a speech-recognition capable SoC. |
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| Learning the ROPES
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2001-09-01 |
| This article describes a new development process, called rapid object-oriented process for embedded systems. |
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| IBIS and SPICE: Modeling languages for the demanding EDA industry
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2000-12-01 |
| This technical article summarizes IBIS and SPICE modeling language, looks at some of the new IBIS developments and then takes a look at the future. |
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| Synthesize SoCs using C-based design flow
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2001-08-01 |
| This is a case study in which an SoC was synthesized for Columns Ltd using a C-based design flow. |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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| Board simulation expands debug scope
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2001-08-01 |
| The paper provides a basic tutorial on board simulation and explains its advantages in improving debugging early in the design stage. |
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| One approach for debugging of modified designs
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2001-03-01 |
| Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one. |
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| Formal verification for IP soft core
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2003-11-17 |
| Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them. |
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Strange modes of transport and other "stuff"
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