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The White Paper on the VHDL (0)
 
EE Times India - total search 28 articles sort by date sort by relevance
Tips for compiling software to gates 2005-07-01
VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages  
Assertion methodologies for Verilog design 2002-01-16
This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL  
A faster way to run Reed Solomon decoders 2001-01-01
This technology news describes the new Reed-Solomon (RS) decoder architecture that can process multiple symbols per clock cycle.  
Peripheral model makes dual run 2001-03-01
With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process.  
Verification firm starts partners program 2001-04-15
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.  
Speed enhancements for Model Tech upgrades 2001-04-15
This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support.  
Developing a design methodology for embedded memories 2001-01-01
Developing a design methodology for  
Syntax raises RTL abstraction level 2001-05-16
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.  
Open source hardware 2002-12-02
This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers.  
Questions for SystemC 2001-05-16
OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement.  
Logic suppliers seek ways to embed FPGAs 2001-03-01
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.  
An integrated approach to PCI verification in SoCs 2001-11-01
This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs.  
The advantage of using logic BIST for ASIC designs 2000-12-01
This technical paper reveals the advantage of using logic BIST for ASIC designs.  
Solving problems early on using co-verification 2004-11-16
Learn the importance and benefits of hardware and software co-verification before the physical design becomes available.  
Co-design method enables speech recognition SoC 2002-09-16
Two STMicroelectronics design engineers use a system-level design flow based on the CoWare N2C method to create a speech-recognition capable SoC.  

Embedded Design India - total search 13 articles
FIFO Dipstick with Warp2 VHDL, CY7C371 2009-04-13
Implement two-dimensional rank order filter 2008-11-26
Tackle team-based FPGA design 2006-03-02
Back to the language roots 2005-01-02
Compiling software to gates 2005-01-01
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EE Times Asia - total search 358 articles
MDP aims for high-intensity processing apps 2010-08-25
Upgraded design suite provides Verilog visualization 2010-08-18
Design flow optimizes partial reconfiguration FPGAs 2010-07-29
Mixed-signal solution directly simulates response surface models 2010-07-26
Processor allows various control, DSP function combo 2010-03-24
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