Implement message-driven testbench for FPGAs
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2004-12-16 |
| Crack the code in improving test implementations--a message driven testbench may just do the trick |
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| Speed up processor verification with testbench infrastructure reuse
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2011-09-01 |
| Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times. |
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| Grasp SystemVerilog testbench debug, analysis
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2008-10-16 |
| The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support |
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| Applying constrained-random verification to microprocessors
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2007-12-10 |
| This article proposes an object-oriented solution for processor verification challenges. |
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| Complex designs call for verification
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2010-06-14 |
| Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging. |
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| Address mixed-signal design issues with assertion-based verification
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2011-11-03 |
| Know the challenges in analogue/mixed-signal verification and learn how assertion-based method can address them. |
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| Moving beyond advanced design geometries
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2008-08-01 |
| Design verification will play a major role in reducing design cost and improving new product yields and product platforms. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| How formal MDV can take out IP integration uncertainty
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2012-01-25 |
| Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics. |
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| Optimising software using TLM virtual platform
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2011-12-07 |
| Find out how transaction level modelling 2.0 was used to produce an executable system model and, subsequently, execute software to analyse functional aspects contributing to overall system level performance. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| Oki, Lexra roll out prototyping boards for SoCs
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2001-04-15 |
| This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs. |
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| Automated video algorithm implementation
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2006-06-02 |
| The article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. A video line filter example is used to illustrate techniques for coding video algorithms. |
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| Flow is shaky for programmable SoCs
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2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
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| Reusing vital verification knowledge with OVM
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2010-01-13 |
| Reuse of legacy-directed test environments is common practice. But with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects. |
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| Testing modems, xDSL and ISDN in a shared environment
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2003-12-16 |
| Dial-up modems, ISDN terminal adaptors and xDSL modems will be more commonly used in a shared environment with the increase in computing power. |
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| Mixed-signal simulation in design, verification
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2005-07-01 |
| Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification |
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| Deterministic simulation of an ARM core
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2001-12-01 |
| This technical article discusses the deterministic and random testing techniques used to verify complex cores such as the ARM946E-S architecture. |
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| Verification reuse ensures predictable design
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2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes. |
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| Using OVM configuration classes
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2010-04-28 |
| This technical paper is a testimony to the fact that configuration classes, when used properly, greatly improve the configurability and adaptability of a verification environment. |
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Strange modes of transport and other "stuff"
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