Implement message-driven testbench for FPGAs
|
2004-12-16 |
| Crack the code in improving test implementations--a message driven testbench may just do the trick |
|
| Grasp SystemVerilog testbench debug, analysis
|
2008-10-16 |
| The task of chip verification is becoming ever so complex as silicon shrinks and SoC designs grow larger. SystemVerilog addresses this challenge by serving as a platform for enabling advanced methodologies and automation. |
|
| Speed enhancements for Model Tech upgrades
|
2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support |
|
| Questions for SystemC
|
2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
|
| Automated video algorithm implementation
|
2006-06-02 |
| The article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. A video line filter example is used to illustrate techniques for coding video algorithms. |
|
| Moving beyond advanced design geometries
|
2008-08-01 |
| Design verification will play a major role in reducing design cost and improving new product yields and product platforms. |
|
| Applying constrained-random verification to microprocessors
|
2007-12-10 |
| This article proposes an object-oriented solution for processor verification challenges. |
|
| Reusing vital verification knowledge with OVM
|
2010-01-13 |
| Reuse of legacy-directed test environments is common practice. But with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects. |
|
| Oki, Lexra roll out prototyping boards for SoCs
|
2001-04-15 |
| This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs. |
|
| Verification firm starts partners program
|
2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
|
| Flow is shaky for programmable SoCs
|
2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
|
| Verification reuse ensures predictable design
|
2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes. |
|
| Testing modems, xDSL and ISDN in a shared environment
|
2003-12-16 |
| Dial-up modems, ISDN terminal adaptors and xDSL modems will be more commonly used in a shared environment with the increase in computing power. |
|
| Deterministic simulation of an ARM core
|
2001-12-01 |
| This technical article discusses the deterministic and random testing techniques used to verify complex cores such as the ARM946E-S architecture. |
|
| Mixed-signal simulation in design, verification
|
2005-07-01 |
| Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification |
|
|
|
|IIC-China
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment