An integrated approach to PCI verification in SoCs
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2001-11-01 |
| This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs |
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| Verification platform for complex designs
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2007-12-31 |
| The article provides an insight on verification problems that semiconductor companies face in today's complex design. It suggests verification platforms to overcome the challenges |
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| Verification IP reuse for complex networking ASICs
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2008-09-18 |
| Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse |
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| Challenge X: Verification testing, validation, and control strategy
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2007-07-19 |
| This article is part of a series featuring the Ohio State University design team's four-year hybrid power train development effort using Model-Based Design tools. It focuses on verification testing, validation and control strategy |
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| Eliminating the problems of dual physical verification
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2003-05-02 |
| A single verification tool that can perform fast interactive verification on cells and blocks, as well as fast and accurate batch verification on full-chip SoCs, is essential to meet today's time-to-market schedules |
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| Formal verification of an MPEG decoder chip
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2001-06-01 |
| This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip |
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| Complex SoCs power intent verification
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2009-05-15 |
| Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level |
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| Tackling physical verification below 90nm
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2005-05-02 |
| The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them |
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| Identification chips bring fingerprint verification a step further
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2006-04-05 |
| A new fingerprint identification chip takes ID verification technology to the next level |
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| Software verification, debug in the MPSoC era
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2007-06-12 |
| A new breed of programming and debug solutions is required to help programmers with the specific software verification challenges in MPSoC |
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| Design with Verification: Not an Oxymoron
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2007-11-05 |
| In SoC development, the relatively new concept and practice of design with verification promises multiple benefits |
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| Solving problems early on using co-verification
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2004-11-16 |
| Learn the importance and benefits of hardware and software co-verification before the physical design becomes available |
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| Speed up processor verification with testbench infrastructure reuse
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2011-09-01 |
| Specialised processor verification IP can free engineers from historical development and maintenance commitments. This liberated time and energy can then allow a renewed focus on verification quality and turnaround times |
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| SystemVerilog enhances assertion-based verification
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2005-06-16 |
| ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how |
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| Verification tool speeds complex IC out the door weeks ahead of schedule
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2002-02-01 |
| This technical article discusses speeding up design and verification of complex ICs without sacrificing quality to beat competition |
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| Quality verification and validation
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2002-06-01 |
| Know the fundamental theory and techniques of verification and validation, and see how they have been successfully applied in the creation of high quality embedded software |
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| Address mixed-signal design issues with assertion-based verification
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2011-11-03 |
| Know the challenges in analogue/mixed-signal verification and learn how assertion-based method can address them |
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| Advancing to true HW/SW co-verification
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2001-11-16 |
| This technical article discusses how advancing to true HW/SW co-verification can enhance embedded systems designs as manufacturers go into deeper submicron processes |
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| Automate formal verification for Open Core Protocol
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2008-09-24 |
| The automation of formal protocol verification using VIPs enables an exhaustive verification of critical IP interfaces |
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| Emulation solves verification challenge
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2007-12-16 |
| Sun Microsystems shares experiences of latest generation hardware-based verification systems used to develop its recently launched Ultrasparc T2 processor |
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| Multi-language verification for multi-site projects, Part 2
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2008-04-12 |
| Read about powerful verification solutions and other issues that may be encountered while designing a solution |
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| Accelerating verification closure for complex SoCs, IPs
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2008-10-24 |
| The complexity of today's SoCs creates the need for advanced verification methods that go beyond simulation-based approaches |
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| Applying constrained-random verification to microprocessors
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2007-12-10 |
| This article proposes an object-oriented solution for processor verification challenges |
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| SystemVerilog reference verification methodology: VMM adoption
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2006-09-04 |
| The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification |
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| Verification challenges of embedded memory devices
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2006-08-14 |
| This article discusses the verification challenges faced by embedded memory designers as the technology moves towards integration |
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| Analogue verification opportunities
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2008-12-24 |
| Read about the techniques for easing analogue/RF systems and circuit design, as well as verification |
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| Address verification issues with scalable methods
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2007-04-10 |
| This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams |
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| Verification reuse ensures predictable design
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2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes |
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| Mixed-signal simulation in design, verification
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2005-07-01 |
| Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification |
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| Accelerate functional verification
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2008-11-25 |
| Read about an approach which promises to simplify the adoption and proliferation of new verification technologies |
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Strange modes of transport and other "stuff"
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