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EE Times India - total search 172 articles sort by date sort by relevance
An integrated approach to PCI verification in SoCs 2001-11-01
This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs  
Verification platform for complex designs 2007-12-31
The article provides an insight on verification problems that semiconductor companies face in today's complex design. It suggests verification platforms to overcome the challenges  
Solving problems early on using co-verification 2004-11-16
Learn the importance and benefits of hardware and software co-verification before the physical design becomes available  
Verification IP reuse for complex networking ASICs 2008-09-18
Here is a verification environment that lays down the methodology blueprint for future ASIC verification projects and stretches the boundary of IP reuse  
Formal verification of an MPEG decoder chip 2001-06-01
This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip  
Identification chips bring fingerprint verification a step further 2006-04-05
A new fingerprint identification chip takes ID verification technology to the next level  
Automate formal verification for Open Core Protocol 2008-09-24
The automation of formal protocol verification using VIPs enables an exhaustive verification of critical IP interfaces  
Complex SoCs power intent verification 2009-05-15
Know the basic elements of low power verification and how a technology enables power-aware verification at the RTL level  
Full-chip verification for building nanometer memories 2002-05-01
Verification tools can greatly facilitate memory design, where designers face a combination of evolving circuit complexity and increasing size in dealing with massive memory arrays  
Automated formal verification for OCP-based IP Cores 2008-01-21
The article discusses the automation of Formal Verification for bus protocols like OCP  
SystemVerilog reference verification methodology: VMM adoption 2006-09-04
The article is the last instalment of a four-part paper about a reference verification methodology that meets the goals for both RTL and system-level verification  
SystemVerilog enhances assertion-based verification 2005-06-16
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how  
Verification tool speeds complex IC out the door weeks ahead of schedule 2002-02-01
This technical article discusses speeding up design and verification of complex ICs without sacrificing quality to beat competition  
Quality verification and validation 2002-06-01
Know the fundamental theory and techniques of verification and validation, and see how they have been successfully applied in the creation of high quality embedded software  
Design with Verification: Not an Oxymoron 2007-11-05
In SoC development, the relatively new concept and practice of design with verification promises multiple benefits  


 
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