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2010-04-19	Virage Logics has sub-systems on its radar
	Virage Logic plans on a makeover as it intends on becoming a supplier of 'sub-systems' that can be quickly embedded in SoCs for its licensees instead of just a provider of a collection of IP cores.
2010-04-16	EDA still has growth option in automotives
	Mentor Graphics execs are of the opinion that automotives still holds out growth options for EDA with the advent of hybrid and electric vehicles.
2010-04-12	IBM: Expect design rule explosion beyond 22nm
	IBM researcher Kevin Nowka described the physical design challenges beyond the 22nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.
2010-04-08	OMAP3530 Easy CUS package PCB escape routing
	This application report shows how to easily route the entire package by first routing one quadrant only and then copying it to the rest of the device.
2010-04-08	EU project to cool IC designs draws electronic firms
	EU-funded Therminator research project aims to enhance existing EDA solutions to enable designers to address temperature issues more effectively using their existing design flows.
2010-03-30	How to deal with formal verification issues
	Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick.
2010-03-29	Cadence takes over EDA start-up Taray Inc.
	To strengthen its position in the design-in of large and complex FPGAs into PC boards, Cadence Design Systems, Inc. has taken over Taray Inc.
2010-03-25	Was EUV the wrong bet for the industry?
	If so, what should it be working on instead? And who will benefit in the long run? Litho experts and executives deliberate on these hot questions.
2010-03-19	Building an EZ-Host/OTG project from start to finish
	This application note describes how to build a simple stand-alone project with these tools that will run in either debug mode or out of an EEPROM.
2010-03-18	Speciality foundries spread their wings
	The speciality foundries Dongbu, MagnaChip, TowerJazz and X-Fab are expanding with new capabilities or alliances.
2010-03-17	Process tech eases ASIC conversion
	Tier Logic Inc. has revealed a few details about a technology that employs a new processing change to build FPGA and ASIC products on a single die.
2010-03-08	Chip design cost to shoot up
	Mentor chairman and CEO Walden Rhines examines the rising cost of chip designing at the Semico Outlook Conference.
2010-03-08	iPDK open standard released
	IC foundries and IDMs can use this standard to build a single iPDK that works with multiple OpenAccess-based custom design tools to cut development costs and support for vendor-specific PDKs.
2010-02-19	The challenges of next-gen automated design tools
	Operators must also deal with issues caused by the multiservice and multitechnology environment. Automated planning tools have proven to be the solution for such challenges.
2010-02-11	Cut design time, cost with early verification
	Verification of algorithm-intensive systems is a long, costly process. In this article, we'll explain three practical approaches to early verification.
2010-02-05	Optimism marks 2010 EDA forecasts
	EE Times lines up estimates and predictions of EDA gurus Walden Rhines, Gary Smith, and Joseph Borel for this year's EDA market.
2010-02-04	Future research avenues in EDA
	Prith Banerjee, senior VP of research and director HP Labs, highlighted promising avenues in EDA with live examples at the VLSI conference.
2010-01-22	Consultant pushes for international EDA roadmap
	Joseph Borel, ex-executive VP in central R&D at STMicroelectronics NV confirms that the EDA industry has a roadmap, but poses the question whether the EDA industry needs an international one.
2010-01-15	Validating netlist reduction, circuit extraction
	A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this technical article.
2010-01-14	Open source: Game changer for hardware industry?
	The panel discussion at the 23rd VLSI conference tackled whether open source can also set a possible trend in the hardware sector.
2010-01-13	Designing for the next upturn
	Mentor Graphics chairman and CEO, Walden Rhines, says that while India¡¯s share in the semiconductor market will grow at 6.4 times the global CAGR, the road ahead is not without its challenges.
2010-01-12	Recession forces focus on core competencies, costs
	Cadence president Lip-Bu Tan says the recent economic recession has focused semiconductor companies on core competencies and boosted collaborative efforts. EDA companies must deliver solutions to cut costs.
2010-01-11	Deliver faster turnaround time with in-design metal fill
	This article discusses the traditional flows and their inherent challenges, establishing the need for an in-design flow that would mitigate those challenges.
2009-12-28	VLSI conference tackles 2010 design challenges
	Dr. Mahesh Mehendale, general chair, International Conference on VLSI Design, talks about the event in 2010. Mehendale is director, Centre of Excellence for Digital Video, TI India, and the only TI Fellow in Asia.
2009-12-17	FPGA dev't kits up SoC design productivity, innovation
	The Virtex-6 FPGA and Spartan-6 FPGA kits are fully equipped with ISE Design Suite 11.4 to shorten development time by enabling developers to focus on competitive differentiation.
2009-12-17	IBM details 3D IC design roadblocks
	IBM Corp. engineer John Knickerbocker lists five roadblocks for 3D devices based on TSVs.
2009-12-02	Address the needs of hardware design flows
	There is a need for a hardware configuration management system that incorporates the features of software configuration management systems, while addressing the needs of different hardware design flows.
2009-11-17	Global conference series makes a pit stop at India
	EE Times-India caught up with Rahul Arya, marketing and technical sales director at Cadence Design Systems (I) Pvt. Ltd, to discuss India's domestic semiconductor industry and to find out what Indian engineers should expect at the CDNLive!.
2009-11-06	Processor packs wide pre-verified DSP options
	Tensilica launched the Xtensa LX3 high-performance dataplane processor (DPU) core optimised for DSP and control in the SoC dataplane.
2009-11-03	Design and application guide for SG6859D
	This application note describes a design strategy for a high-efficiency compact flyback converter. Design considerations and mathematical equations are presented, as well as the guidelines for PCB layout.
2009-09-17	Mentor CEO: EDA recovery will take a while
	Mentor CEO said optimism in the IC industry is spreading to the EDA sector, though most design companies are still limiting new spending.
2009-08-06	EDA 'big three' execs tackle recession
	The "big three" of EDA held a panel session at Design Automation Conference (DAC) on the future of EDA and agreed that this is not "your father's recession."
2009-06-23	Upgraded EDA tool adds flow-routing option
	Pulsic Ltd has introduced an upgrade to its physical chip design software suite, Unity 2009.1.
2009-06-12	Nokia eyes Web designers with new tools
	Nokia hopes to open a floodgate for Web developers to extend existing content to Nokia's mobile platform.
2009-05-26	Tools roll to support NXP's LPC176x series
	SEGGER has released middleware and debugging products for the LPC176x series of Cortex-M3 based MCUs.
2009-05-25	IAR to provide devt tools for SuperH MCUs
	IAR Systems will develop a version of IAR Embedded Workbench for SH-2A core MCUs from Renesas.
2009-05-21	Tools aim to speed design process
	At its European user meeting CDNLive, Cadence has unveiled two tools that attack on different points.
2009-05-08	Physical verification tools offer free trial
	Magma Design Automation has introduced the Quartz DRC and Quartz LVS 2009.05 physical verification tools.
2009-04-28	Photoresist market gets boost from litho tools
	The trend towards advanced 193nm DUV lithography tools is affecting the market shares of photoresist suppliers.
2009-04-17	Challenges, solutions for EDA start-ups
	Read about the challenges and growth opportunities for EDA start-ups.
2009-04-17	Parallel computing tools get new versions
	The MathWorks has announced new versions of its MATLAB parallel computing products.
2009-04-15	GPUs vs. CPUs for EDA simulations
	There are three ways to make the simulation go faster: better algorithms, faster processor clocks and parallelism.
2009-03-23	EDA tools upgraded for 64-bit computers
	Tanner EDA has announced the new version of its interoperable and easy to use electronic design software.
2009-03-20	New tools address SoC, FPGA markets
	Dafca's ClearBlueXpress and ClearBlueFPGA incorporate the company's patented, reprogrammable fabric.
2009-03-19	What are next gen planning tools?
	Read about network planning tools which are emerging as a core elements of any efficient migration strategy.
2009-03-19	Network-on-chip EDA software gets version 3.0
	Silistix has added the capability to create local clocked networks to its Chainworks EDA software.
2009-03-13	Optical test instrument touts new analysis tools
	Agilent has announced what it claims is the industry's first time-domain based optical modulation analyser.
2009-03-02	Jasper launches new verification tools
	Jasper Design Automation said it is automating IC design verification routines with a new suite of tools.
2009-02-24	Synopsys to dominate EDA market?
	Synopsys says its relative strength will buttress trends that have been working in its favour, driving even more marketshare its way.
2009-02-19	EDA software for 3-D stacked ICs unveiled
	3D PathFinding extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform.
2009-02-12	Verification tools tout faster runtime
	The latest Quartz DRC and Quartz LVS from Magma offer significant runtime improvement.
2009-02-11	MCU tools ease design of low-power apps
	TI expanded its portfolio of development tools to help designers create energy-efficient applications quickly.
2009-02-06	Mentor CEO contests pessimism in EDA
	In a recently delivered speech, Walden Rhines of Mentor Graphics pointed to a bright future for EDA, despite the doom-and-gloom that surrounds the industry.
2009-02-04	Comment: Negativism in the EDA industry
	The EDA industry is suffering because that world economy is based on consumerism; and consumers have run out of money.
2009-02-02	Design tools ease RF systems design
	ADI has released the ADIsimRF and ADIsimPLL Version 3.1 free downloadable software design tools.
2009-01-29	Mentor provides EDA tech to Freescale
	The select EDA technologies are designed to enhance the manufacturability and testability of semiconductors.
2009-01-28	Intel releases updated concurrent C/C++ tools
	Intel has released version 0.3.0 of its Concurrent Collections for C/C++, downloadable from the company's site.
2009-01-22	Comment: EDA industry status report
	There is always time to fine tune the future, as it becomes the present and near past, anyway.
2009-01-22	Algorithmic synthesis tools increase performance
	Synfora debut new versions of the PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools.
2009-01-21	Formal verification tools roll for beginners
	OneSpin has amended its software and packaged it in a way that supports a step-by-step approach for beginners.

2009-01-14	EDA revenue in Q3 was down 11%
	EDA revenue in the third quarter of 2008 was about Rs.6,305 crore ($1.26 billion), says EDAC.
2009-01-12	Analyst: EDA market improvement in Q3
	A market research firm projects EDA product and maintenance revenue to rise about 1 per cent in 2009.
2009-01-12	VLSI 2009 unveils results of EDA contest
	The VLSI Society has successfully held its EDA software and design contest at this year's conference.
2009-01-02	Sub-100nm tech brings EDA opportunities
	Know the challenges in sub-100nm design and the tools that could improve designer's productivity.
2008-12-12	Software provides equalisation tools
	Agilent has unveiled the serial data equalisation software for its Infiniium 90000A Series oscilloscope.
2008-12-11	Software tools extend support for nano FPGAs
	Libero IDE 8.5 also offers high-speed multiplier instantiation for RTAX-DSP applications.

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