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What is VHDL?

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.

VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a methodology and a toolset are essential for the effective use of VHDL.

Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part of the language.

VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is the language, you choose the tools, and the methodology... well, I guess that's where Doulos come in to the equation!

Source: doulos
Technical Archives related to VHDL:
Speed up your RTOS synthesis 2008-04-01
To investigate the use of software synthesis technology, engineers set out to use a software synthesis tool to generate an embedded RTOS. Performance measurements were also taken to see how well the synthesised system worked.
Build efficient datapath designs 2005-10-03
This article proposes RTL coding guidelines and a context-sensitive RTL datapath synthesis for improving design productivity
Tips for compiling software to gates 2005-07-01
VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages
SystemVerilog enhances assertion-based verification 2005-06-16
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how
Lower costs through design tool performance 2005-03-16
The ISE software has capabilities that reduce design and verification times, attaining design closure faster
Generating event-based system power simulation 2005-03-01
To enable research in power computing, a simulation infrastructure that allows accurate power and performance for programs and operating systems is needed
Solving problems early on using co-verification 2004-11-16
Learn the importance and benefits of hardware and software co-verification before the physical design becomes available.
Formal verification for IP soft core 2003-11-17
Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them.
Open source hardware 2002-12-02
This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers.
Co-design method enables speech recognition SoC 2002-09-16
Two STMicroelectronics design engineers use a system-level design flow based on the CoWare N2C method to create a speech-recognition capable SoC.
Mastering full-custom layout design 2002-02-16
This technical article assists readers in defining the various flavors of full-custom layout design for them to choose the right type of tool for the right type of job.
Assertion methodologies for Verilog design 2002-01-16
This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL
An integrated approach to PCI verification in SoCs 2001-11-01
This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs.
Learning the ROPES 2001-09-01
This article describes a new development process, called rapid object-oriented process for embedded systems.
Synthesize SoCs using C-based design flow 2001-08-01
This is a case study in which an SoC was synthesized for Columns Ltd using a C-based design flow.
New Products related to VHDL:
Aldec introduces multi-threaded VHDL compilation 2007-12-24
Aldec has announced the release of Active-HDL 7.3 that includes multi-threaded HDL compilation, new waveform viewer and expanded VHDL 2006 construct support
Devt kit for customisable ARM9-based MCUs debuts 2007-09-20
Atmel has introduced its FPGA devt kit that allows the simultaneous development and emulation of both the ARM9 software and FPGA Verilog/VHDL designs
IC emulator handles 10 crore gates at 20MHz 2007-01-24
EVE SA has claimed to have developed the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz.
Yogitech announces OCP verification component 2006-10-04
Yogitech SPA, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol UVC.
ESL tool tames one tough task: On-chip register design 2005-08-29
Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling.
EDA platform trims design time in half 2008-09-17
Agilent has introduced SystemVue 2008, an EDA platform for electronic system-level design.
Ultra low-power FPGAs set new standard 2008-06-12
SiliconBlue announces a new class of single-chip, ultra low-power FPGA devices have unprecedented ASIC-like logic capacity for battery-powered, handheld consumer applications.
Xilinx adds embedded, DSP, RT debug design flows to tool 2006-01-16
Xilinx Inc. has announced that the availability of the ISE WebPACK 8.1i programmable logic design tool, which includes all the features of ISE Foundation with full support for embedded, DSP and real-time debug design flows.
Simulator supports Open IP Encryption 2006-07-14
Aldec says its new version of the Riviera simulation tool supports design flows based on Synplicity's Open IP Encryption Initiative.
Reference designs extend battery life 2008-11-18
The new PowerWise reference designs aim to empower design engineers to speed through the design process.
ESL starter kit assists in FPGA design 2006-03-17
Celoxica has announced availability of its ESL starter kit, which combines the DK Design Suite of C-based design and synthesis tools, with an RC10 Xilinx FPGA development board.
Xilinx expands functionality of PinAhead tech 2007-08-17
Xilinx has announced the immediate availability of version 9.2 of its PlanAhead hierarchical design and analysis design tool.
Mathworks' RF Toolbox includes signal integrity capability 2006-12-15
The Mathworks is rolling out the RF Toolbox 2, which adds time-domain capabilities to this Matlab add-on package. As a result, the company said, engineers can significantly reduce the time needed to develop I/O circuitry for high-speed digital systems.
ON2 unveils multi-format hardware video decoder 2008-02-14
On2 Technologies has announced the release of the Hantro 8190 multi-format configurable hardware RTL video decoder for mobile phones.
Mentor, MathWorks collaborate on optimised FPGA design flow 2007-11-23
Mentor Graphics and MathWorks have collaborated on HDL generated by MathWorks Simulink HDL Coder in Mentor?s Precision suite of advanced synthesis products to provide a rapid path from Simulink models to FPGA implementation.
News & Trends related to VHDL:
Accellera approves new VHDL standard 2006-07-26
Accellera's members have approved a new VHDL standard, a VHDL Applications Programming Interface (API) known as VHPI on June 28
Revised VHDL spec boosts IP security 2006-11-16
The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption
VDA VHDL-AMS models run in Synopsys' simulator 2006-04-28
Synopsys has announced that it has qualified the VHDL-AMS models to run in the Synopsys Saber simulator for use by automotive OEMs and suppliers
Synopsys donates power management tech to EDA org 2006-09-21
Synopsys Inc. has donated power management technology to Accellera. The donation includes power management commands, SystemVerilog constructs, VHDL constructs and the Switching Activity Interchange Format
Engineer designs tool to generate logic specs 2006-02-03
After working in labs designing fault-tolerant flight-control systems, Dave McFarland came to realise that there's no good way to specify logic and look at all the possible combinations. So he built a tool to handle the job.
Sub-$200 tools power 'farms' for verification 2005-09-01
Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck.
Denali spreads new word in ESL mart 2005-10-03
With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market.
Accellera launches UCI to define verification metrics 2007-02-02
Accellera standards organisation has launched the UCI to define standards that enable the sharing and analysis of coverage data by different tools during the verification process.
VLSI trends: Scaling CMOS to its limit 2008-02-16
Over 1,000 technologists, researchers, experts and students converged in the city of Hyderabad on Jan. 5, 2008 to attend the VLSI Conference. Dipti Agarwal reports.
OCP-IP to announce interface for virtual prototyping 2008-03-10
At the DATE conference in Munich the OCP-IP will announce a new standard interface for a virtual prototyping debugger.
Survey finds verification tool use largely unchanged from 2004 2005-10-27
The 2005
Re-synthesis solution offers area, speed, power benefits 2007-05-28
Nangate Inc. has claimed that its Design optimiser solution is capable of creating an optimised gate-level design with area, speed or power benefits.
Vendors support SystemVerilog synthesis 2006-04-19
Synthesis vendors are strongly supportive of a proposed standard SystemVerilog synthesis subset.
Industry likely to support both CPF, UPF 2007-03-27
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF.
IEEE approves Cadence's 'e' language 2006-06-01
The IEEE has approved Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support.
Application Notes related to VHDL:
Using hierarchy in VHDL design 2001-03-22
This application note describes VHDL's features, which are specifically designed to make hierarchical design both simple and powerful, and presents a simple example of how these features might be used
Getting started converting .ABL files to VHDL 2001-03-20
This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL
Abel-HDL vs. IEEE-1076 VHDL 2001-03-20
This application note compares and contrasts the complexity and basic features of Abel-HDL with those of IEEE-1076 VHDL
FIFO Dipstick using Warp2 VHDL and the CY7C371 2001-03-21
This application note presents a method by which FIFOs of any size may be monitored by an external PLD that will then generate all of the flags necessary for most FIFO applications.
ispLSI 8000V Family VHDL Code Examples 2002-10-11
This application note talks about the ispLSI8000V family architecture features and includes coding examples designed to allow the user to take advantage of its hardware capabilities.
Building crosspoint switches with CoolRunner-II CPLDs 2002-06-28
This application note provides a functional description of the VHDL source code for a NxN digital crosspoint switch using a 128-macrocell CoolRunner-II CPLD
An introduction to active-HDL Sim 2001-03-28
This application note provides a brief discussion to the Active-HDL Sim functional simulator. The discussion includes installing/uninstalling the simulator, creating an 1164/VHDL simulation model, the simulation process, and applying stimulus
Method to instantiate and use a core in Warp with Cypress CPLDs 2001-03-20
This application note describes in detail how customers can incorporate cores in their system-level designs. It contains a detailed description of the steps required to instantiate VIF files in both VHDL and Verilog designs
Making designs 50% smaller 2008-11-12
Here's a design technique that can make a difference in the size and the performance of your FPGA design.
Interfacing the DS2760 1-Wire High Precision Li-Ion Battery monitor in a Microcontroller Environment 2002-12-06
Interfacing the DS2760 1-Wire High Precision Li-Ion Battery monitor in a Microcontroller Environment
CoolRunner-II for selecting video source 2008-11-10
Know how CoolRunner-II CPLD works as a logical switch that can select between different MPEG video sources.
DDR SDRAM DIMM interface for Virtex-II devices 2004-12-09
DDR SDRAM DIMM interface for Virtex-II devices
Using a UART to implement a 1-Wire Bus Master 2003-05-27
Using a UART to implement a 1-Wire Bus Master
An Introduction to active-HDL FSM 2001-03-22
This application note provides an introduction to the Active-HDL FSM (finite state machine) editor, while highlighting key features of the software and illustrating the steps required to create a state machine.
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