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RF/Microwave  

Modeling and simulation of jitter in PLL frequency synthesizers

Posted: 26 Apr 2001  Print Version  Bookmark and Share Subscribe

Keywords: cadence  pll  frequency synthesizer  simulator  simulation tool 

[Summary of tips] This application note presents a methodology for predicting the jitter performance of a PLL using accurate and efficient simulation that is within the behavioral level.View the PDF document for more information.
 

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