T&M 
Wrestling with functional verification
Keywords: functional verification logical design flow acceleration emulation test bench
[Summary of tips] If functional verification already consumes most of the IC logical design flow, as some studies suggest, what's going to happen as chip complexity reaches 10 million or 100 million gates?The answer is sheer chaos—unless the functional-verification process can be made more manageable. Coverage-driven verification can help ......Please login or register with us to view this article>>
|
Not a registered user?
Register FREE to view unlimited features, tutorials and products, and enable any content alert service!
 |
Already registered? Login to view complete content.
|
Comment on "Wrestling with functional verificati..."
Visitor0205
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Most Popular Articles
Search EE Times India
Max's Cool Beans
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
