Revised VHDL spec boosts IP security
Keywords: Accelera VHDL Verilog design language IEEE
[Summary of tips] The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for intellectual property (IP) encryption.Though ......|
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