EDA/IP 
Testing complex systems on chip
Keywords: SoC test ATPG static timing analysis BIST fault model
[Summary of tips] The increasing complexity of SoCs has posed new challenges in the way we test these designs. A typical SoC could have random logic, special cores, large and small memories interleaved throughout the design, IP and programmable logic, and every functional component in the device may require its own test strategy.View the PDF doc......Please login or register with us to view this article>>
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