Low power challenges push for system-level EDA
Keywords: low-power design Common Power Format Unified Power Format Cadence Synopsys
[Summary of tips] Facing mounting challenges of low-power design especially in complex mixed-signal SoC designs, designers are expecting a higher degree of system-level capability in EDA tools.There are strong expectations from tools to analyse and optimise power at the architecture level, extend low-power design techniques for analogue/mixed-si......|
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