Global Sources
EE Times-India
 DAC 2010 coverage   Academia on employability gap   VLSI Design Conference 2010
EE Times-India > EDA/IP
 
 
EDA/IP  

STARC design flow incorporates Cadence tech

Posted: 24 Jan 2008  Print Version  Bookmark and Share Subscribe

Keywords: Common Power Format  reference flow  Si2 

[Summary of tips] Cadence Design Systems Inc. announced that Japan's Semiconductor Technology Academic Research Centre (STARC) has released its next-generation ultralow power PRIDE reference flow V1.5, incorporating the Common Power Format (CPF)-based Cadence Low-Power Solution. This reference flow also includes key litho-aware manufacturing (DF......
Please login or register with us to view this article>>
 

Comment on "STARC design flow incorporates Caden..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Highly Recommended Articles

Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut