EDA/IP 
Practical Power Network Synthesis For Power Gating Designs
Keywords: power gating power network synthesis sleep transistors SoC
[Summary of tips] Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoid......Please login or register with us to view this article>>
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