Global Sources
EE Times-India
 DAC 2010 coverage   Academia on employability gap   VLSI Design Conference 2010
EE Times-India > EDA/IP
 
 
EDA/IP  

Early power analysis with CPF

Posted: 31 Oct 2008  Print Version  Bookmark and Share Subscribe

Keywords: SoC  PowerTheater  CPF 

[Summary of tips] There are two challenges facing SoC designers who want to perform power analysis and management. First, and most obviously, designers need to verify that their design intent is captured in CPF results in a design that meets power budgets for all modes of operation. Second, designers exploring architectural alternatives at the R......
Please login or register with us to view this article>>
 

Comment on "Early power analysis with CPF"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Highly Recommended Application Notes

Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut