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Aldec rolls out ALINT 2008.10
Keywords: ASIC design HDL source code VHDL Verilog
[Summary of tips] Aldec Inc. has released the ALINT 2008.10, a VHDL and Verilog Design Rule Checking Tool used to analyse HDL source code against a comprehensive set of ASIC design guidelines for early bug detection. ALINT reduces risk when developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early......Please login or register with us to view this article>>
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