Global Sources
EE Times-India
 DAC 2010 coverage   Academia on employability gap   VLSI Design Conference 2010
EE Times-India > EDA/IP
 
 
EDA/IP  

Optimising architecture-oriented C, Part 2

Posted: 03 Feb 2009  Print Version  Bookmark and Share Subscribe

Keywords: loop mechanisms  memory  hardware 

[Summary of tips] Part 1 of this series looks at architecture-oriented C optimisation. It shows how C optimisations can take advantage of zero overhead loop mechanisms, hardware saturation, modulo registers, and more. This part looks at optimising C to account for memory alignment, cache features, endianness, and application specific instruction......
Please login or register with us to view this article>>
 

Comment on "Optimising architecture-oriented C, ..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Highly Recommended Application Notes

Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut