EDA/IP 
Sign-off flow shortens design cycle
Keywords: sign-off flow RF design kit EDA tools silicon foundry
[Summary of tips] The disadvantage is a chip maker is tied to specific tools or design methodologies. The flow consists of several different pieces. Synopsys Inc. provides the place and route tools. Synopsys and Cadence Design Systems Inc. provide the signoff timing analysis (STA) tools. Apache Design Solutions Inc. provides the electro-migratio......Please login or register with us to view this article>>
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