EDA/IP 
IC verification: Coverage vs. qualification
Keywords: verification functional coverage simulation
[Summary of tips] Verification is an expensive activity in IC development. It is also a difficult activity to complete efficiently. Coverage-driven verification has been widely adopted in the industry, but is also widely accepted as being an incomplete measurement of verification. To find a design bug, three things must occur during the executio......Please login or register with us to view this article>>
|
Not a registered user?
Register FREE to view unlimited features, tutorials and products, and enable any content alert service!
 |
Already registered? Login to view complete content.
|
| Related Articles | Editor's Choice |
- Tool eases verification of MEMS devices
- Address mixed-signal design issues with assertion-based verification
- Perform ROM verification using Checksum
- Perform ROM verification using CRC-CCITT
- Speed up processor verification with testbench infrastructure reuse
- ARM buys processor verification firm Obsidian
Comment on "IC verification: Coverage vs. qualif..."
Visitor0210
(To avoid code verification, simply login or register with us. It is fast and free!)
|
||||||||||||||
|
||||||||||||||
 |
Top Ranked Articles
Most Popular Articles
Search EE Times India
Max's Cool Beans
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
