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SEU techniques for Virtex-5 devices

Posted: 23 Jun 2009  Print Version  Bookmark and Share Subscribe

Keywords: Virtex-5  single event upsets  FPGA 

[Summary of tips] Xilinx devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events.This application note is accompa......
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