Global Sources
EE Times-India
 Outlook 2010   VLSI Design Conference 2010   Cornerstone of success in 2010
EE Times-India > Manufacturing/Packaging
 
 
Manufacturing/Packaging  

IBM details 3D IC design roadblocks

Posted: 17 Dec 2009  Print Version  Bookmark and Share Subscribe

Keywords: 3D  through-silicon via  chip design 

[Summary of tips] Spotlight is now on the 3D chip design.IC makers are exploring the possibly of stacking current devices in a 3D configuration. Experts define a true 3D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips......
Please login or register with us to view this article>>
 

Comment on "IBM details 3D IC design roadblocks"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Resources

Android faces hurdles in low-cost arena

Android 4.0's step-up in memory and processor demands will make it less attractive in the low-cost smartphone market...

Showcasing the Rs.1,121.08 computer

A UK-based foundation claims the Raspberry Pi, a Rs.1,121.08 ($25) computer board...

Mobile processors boom

Strong growth of mobile devices up until 2016 will drive an exponential growth for mobile processors...

Google, Samsung team on Android 4.0

Samsung's Galaxy Nexus is the first smartphone launched with Google latest Android 4.0 OS...

Intel withdraws Smart TV chip business

Intel reveals plans to withdraw its Smart TV chip business.

Max's Cool Beans

Clive Maxfield Strange modes of transport and other "stuff"

Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut