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PLD architecture trades off time with circuit density

Posted: 03 Mar 2010  Print Version  Bookmark and Share Subscribe

Keywords: 3D  PLD  FPGAs 

[Summary of tips] Bismuth: In essence, we are trading space for time and density for performance."We are doing nothing exotic with the process," explained Alain Bismuth, VP, marketing. "We are using TSMC's standard 40nm process in a standard high-performance package—there is nothing like chip stacking or 3D silicon." Spacetime devices inst......
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