EDA/IP 
Tools bridge chip design, verification with shared database
Keywords: behavioural indexing chip design formal verification RTL modelling
[Summary of tips] Jasper Design Automation Inc. has upgraded its ActiveDesign and JasperGold tools with capabilities that the company claims bridge the divide between chip design and verification by sharing a common, persistent knowledge base.Jasper's ActiveDesign with behavioural indexing lets users design, concurrently modify and verify their ......Please login or register with us to view this article>>
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