Engineers discuss 3D chip standard
Keywords: 3D chip standard Through-Silicon Vias Semicon West
[Summary of tips] Participants of a Semicon West 2010 workshop took the first crack at outlining standards for 3D silicon chips to address design, yield and cost problems.Linking stacks of chips with tiny silicon vias promises smaller devices that need less power to deliver greater performance for a variety of applications. But engineers said a ......
|
Not a registered user?
Register FREE to view unlimited features, tutorials and products, and enable any content alert service!
 |
Already registered? Login to view complete content.
|
| Related Articles | Editor's Choice |
Android faces hurdles in low-cost arena
Android 4.0's step-up in memory and processor demands will make it less attractive in the low-cost smartphone market...
Showcasing the Rs.1,121.08 computer
A UK-based foundation claims the Raspberry Pi, a Rs.1,121.08 ($25) computer board...
Mobile processors boom
Strong growth of mobile devices up until 2016 will drive an exponential growth for mobile processors...
Google, Samsung team on Android 4.0
Samsung's Galaxy Nexus is the first smartphone launched with Google latest Android 4.0 OS...
Intel withdraws Smart TV chip business
Intel reveals plans to withdraw its Smart TV chip business.
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
