Engineers discuss 3D chip standard
Keywords: 3D chip standard Through-Silicon Vias Semicon West
[Summary of tips] "When we first started 3D processing, wafers were showing up broken or chipped," Rudack said. "I am now violating Sematech standards about 25 times a day," he quipped.Wafer bonding and thinning processes used to make 3D ICs create wafers that are larger or smaller than the Sematech M1.15 standard for 300mm wafers. As a result 3......
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